First Open-Source Industry-Specific Model for Semiconductors

We use MixedWM38, the mixed-type wafer defect pattern dataset for wafer defect pattern regcognition with visual transformers.

Lithography defect prediction for microchip manufacturing optimization with machine learning model

Practical example from the SPIE short course "Data Analytics and Machine Learning in Semiconductor Manufacturing: Applications for Physical Design, Process and Yield Optimization"

Data-Driven Optimization of Semiconductor Processes and Forecasting

HackerFab IITB's website and documentation

MEMS patent

WaferDetect is an AI-powered wafer-map defect intelligence platform for semiconductor fabs that segments failure patterns in silicon wafers with AI, diagnoses their root causes and possible errors in the manufacturing process, and quantifies the wafer map die yield loss in dollars.

Mask-aware wafer defect classification using a DenseNet-based CNN with explicit geometry masking and Grad-CAM explainability.

Czochralski Apparatus for Modeling Efficient Lattice growth

Semiconductor Process Control (ECE6455-A) @ Georgia Institute of Technology, Atlanta, GA, USA

klayout square array of auto-labeled alignment marks

# Casimir Ultra-Smooth Fabrication Platform (Research)

High-fidelity process simulation dashboard built in Python. Features include Deal-Grove thermal oxidation (calibrated to BYU standards), Gaussian ion implantation profiling, and selective etch rate modeling with real-time cross-sectional visualization.

This repository contains Silvaco simulation code and Python code for easy data analysis. Do not forget to install the required Python modules in your system.

A Minecraft mod adding realistic semiconductor manufacturing.

Micron AI Challenge 2025

JMP-based lithography focus-dose process window and yield analysis using public exposure and inspection data.

Calculating semiconductor chip yield against defect density using a Monte Carlo simulation is a common approach to assess the impact of defects on chip manufacturing. In this simulation, we'll randomly generate defect locations and evaluate chip yield based on specified criteria.

Deal–Grove thermal silicon-dioxide growth calculator