pipelined-cpu

Here are 5 public repositories matching this topic...

Zhungg / rv32i-cpu-openlane

RV32I 5-stage pipelined CPU core implemented in SystemVerilog and taken through a complete Sky130A RTL-to-GDSII flow using OpenLane 2 and OpenROAD.

Updated Aug 13, 2026
Verilog

soumajit-m / 8086-pipelined-core-verilog

Star

Synthesizable Intel 8086 pipelined core in Verilog with decoupled BIU/EU, 6-byte prefetch FIFO, 20-bit segmentation, and Artix-7 FPGA synthesis.

fpga rtl verilog vivado computer-architecture icarus-verilog gtkwave intel-8086 digital-design 8086 cpu-core pipelined-cpu

Updated Oct 13, 2026
Verilog

WarGodAKJ / 32bit-pipelined-cpu-verilog

Star

Five-stage 32-bit pipelined CPU in Verilog with hazard detection, forwarding, simulation, synthesis, implementation, and FPGA bitstream generation.

fpga hardware processor rtl computer-engineering verilog vivado computer-architecture digital-design pipelined-cpu

Updated Sep 1, 2026
Verilog

SudheerVadrevu / simplified-risc-xl

Star

A fully modular, pipelined 32-bit RISC processor built using Verilog with testbenches and ASIC-ready structure. Part of master's coursework at BTH.

verilog digital-logic computer-architecture risc-processor asic-design pipelined-cpu bth-sweden

Updated Jul 15, 2025
Verilog

SalehHijazi / MIPS-Pipeline-CPU

Star

A synthesizable 5-stage pipelined MIPS CPU and SoC architecture implemented in Verilog. Features advanced hardware hazard mitigation (data forwarding & load-use stalling), an expanded ISA (JAL, shifts, logical immediates), self-checking testbenches, and Xilinx FPGA readiness.

verilog digital-logic computer-architecture mips-processor hardware-verification rtl-design soc-design pipelined-cpu fpga-ready

Updated Jan 3, 2026
Verilog

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