Synthesizable Intel 80286-compatible CPU core in SystemVerilog, with project-owned microcode, real and protected mode, and verification against hardware-captured 80286 test data.
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Oct 15, 2026 - SystemVerilog
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cpu-core
Here are 9 public repositories matching this topic...
Parallel Merge Sort is an optimized sorting algorithm that leverages parallel processing to enhance the performance of the traditional merge sort. This project implements a parallel version of the merge sort algorithm using Python, allowing for efficient sorting of large datasets.
multiprocessing software-development parallel-processing multiprocessor profesional-development cpu-core
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Aug 22, 2024 - Jupyter Notebook
This is where I am putting first RISC-V RV32I single-cycle processor (in development)
cpu fpga processor riscv rtl verilog systemverilog computer-architecture soc formal-verification yosys risc-v digital-design rv32i verilator symbiyosys cpu-core oss-cad-suite riscv-formal riscv-tests
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Aug 4, 2026 - SystemVerilog
Stoic-V: a deterministic RV32IM + Zba/Zbb/Zbs + Zicsr (M-mode) RISC-V soft core in SystemVerilog. No caches, speculation, or branch prediction, so timing is operand-independent and WCET is statically analysable. Drop-in replacement for the AMD MicroBlaze-V via the LMB v10 interface; closes 250 MHz on UltraScale+.
real-time fpga riscv systemverilog lmb wcet deterministic hdl risc-v soft-core rv32 ultrascale hard-real-time cpu-core microblaze-v
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Jun 13, 2026 - SystemVerilog
Synthesizable Intel 8086 pipelined core in Verilog with decoupled BIU/EU, 6-byte prefetch FIFO, 20-bit segmentation, and Artix-7 FPGA synthesis.
fpga rtl verilog vivado computer-architecture icarus-verilog gtkwave intel-8086 digital-design 8086 cpu-core pipelined-cpu
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Oct 13, 2026 - Verilog
Basic CLI tool for switching Linux CPU governors per core or system-wide.
linux bash cli performance cpu bash-script cpu-cores cpufreq cpu-governor system-tool cpu-performance cpu-core cpu-core-management
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Apr 16, 2026 - Shell
Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
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Jul 31, 2026 - SystemVerilog
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