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[HIP] Add offload PGO tiled matmul E2E test#366

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[HIP] Add offload PGO tiled matmul E2E test#366
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[HIP] Add offload PGO tiled matmul E2E test

Add a tiled matrix multiply kernel that demonstrates the offload PGO
workflow on AMDGPU. The kernel uses a large per-thread sub-tile
(configurable via -DTH_M and -DTH_N) with LDS-based cooperative tile
loading, creating natural register pressure that exceeds the VGPR
budget and causes spills. Boundary tile handling creates biased
branches that PGO can optimize by guiding the register allocator to
reduce spills on the hot path.

Sub-tile sizes are tunable per architecture to induce spills on GPUs
with different register file sizes.

Two tests are registered:

  • pgo-tiled-matmul: correctness test (compile + run + verify)
  • pgo-tiled-matmul-pipeline: full PGO pipeline test
    (baseline -> instrument -> collect -> merge -> PGO build -> compare)

The pipeline test verifies that the full -fprofile-generate /
-fprofile-use workflow completes successfully and reports the
performance difference for information.

@yxsamliu yxsamliu requested review from jmmartinez and jplehr March 10, 2026 14:03
Comment thread External/HIP/pgo-tiled-matmul.hip Outdated
Comment thread External/HIP/workload/pgo/test_pgo_matmul.sh.in Outdated

@jmmartinez jmmartinez left a comment

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Looks good to me but I'll JP have the final word.

@jplehr jplehr left a comment

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LG
Just comments about the GPU arch of the bots.

Reporting the actual PGO speed-up just for information purpose is good.

Comment thread External/HIP/pgo-tiled-matmul.hip Outdated
Comment thread External/HIP/workload/pgo/test_pgo_matmul.sh.in Outdated
@yxsamliu yxsamliu force-pushed the amd/dev/yaxunl/pgo-tiled-matmul-test branch from 7e4c1ad to 1edfa31 Compare June 10, 2026 02:26
Add a tiled matrix multiply kernel that demonstrates the offload PGO
workflow on AMDGPU. The kernel uses a large per-thread sub-tile
(configurable via -DTH_M and -DTH_N) with LDS-based cooperative tile
loading, creating natural register pressure that exceeds the VGPR
budget and causes spills. Boundary tile handling creates biased
branches that PGO can optimize by guiding the register allocator to
reduce spills on the hot path.

Sub-tile sizes are tunable per architecture to induce spills on GPUs
with different register file sizes.

Two tests are registered:
- pgo-tiled-matmul: correctness test (compile + run + verify)
- pgo-tiled-matmul-pipeline: full PGO pipeline test
  (baseline -> instrument -> collect -> merge -> PGO build -> compare)

The pipeline test verifies that the full -fprofile-generate /
-fprofile-use workflow completes successfully and reports the
performance difference for information.
@yxsamliu

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Gentle ping. The llvm-zorg PR needed by this test has landed now: llvm/llvm-zorg#868

All review comments here have been addressed and resolved. Could you take another look when you get a chance?

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3 participants