soc/intel/cannonlake: skip CPU replacement check on CML

[jackadam1981]

Summary

Add a Cannonlake/Comet Lake platform config knob for the FSP-M SkipCpuReplacementCheck test UPD, then enable it at the Google Puff baseboard level.

On KAISA, cold boots were spending about 30 seconds inside FspMemoryInit even though RW_MRC_CACHE existed and both DIMMs matched the cached SPD data. Warm reboots reused the cache and completed memory init in roughly 40 ms. Enabling this option at the mainboard level keeps FSP-M on the no-configuration-change path for this case.

Implementation

• Add SkipCpuReplacementCheck to soc_intel_cannonlake_config.
• Pass that platform config value into FspmTestConfig.SkipCpuReplacementCheck.
• Enable the option in google/puff baseboard devicetree.cb.

Validation

Tested on Acer Chromebox CXI4 / KAISA with a Comet Lake build based on MrChromebox-2603.

Before this change:

• Cold power-on: FspMemoryInit took about 30.5 s.
• Warm reboot: FspMemoryInit took about 40 ms.
• Logs showed SPD_CACHE: DIMM0 is the same, DIMM1 is the same, but the MRC cache was updated after the slow cold boot.

With this change:

• Cold power-on: FspMemoryInit took about 46 ms.
• Warm reboot: FspMemoryInit took about 41 ms.
• Logs showed SPD_CACHE: DIMM0 is the same, DIMM1 is the same, and MRC: 'RW_MRC_CACHE' does not need update.

Build verification after moving this to platform/mainboard config:

• Built KAISA release UEFI/iPXE-only ROM in coreboot/coreboot-sdk.
• Build log: /home/jack/coreboot_build/out/logs/build-kaisa-2603-release-ipxe-only-skipcpu-platformcfg-20260601-155458.log
• ROM SHA256: 214ebe3926b0727c9e37060b5acdf71f7a6fd26342458bb305d74ede6cfa73ba

[MrChromebox]

I'll need to hook it up to the platform config and set it at the mainboard level in order to upstream, but thanks for identifying the root cause

[jackadam1981]

Reworked this to go through platform config and enable it at the google/puff baseboard level. The SoC code now passes \config->SkipCpuReplacementCheck\ into FSP-M instead of hardcoding it. Rebuilt KAISA successfully; updated the PR description with the new build log/hash.

[MrChromebox]

I actually rework this locally to align more closely with alder lake, so that the default is to skip the check and that boards can enable the check as needed. this way we're not setting something for every board that should be disabled by default

[MrChromebox]

https://review.coreboot.org/c/coreboot/+/93152

[MrChromebox]

the patch above has been merged upstream and picked back into 2603

[MrChromebox]

closing as improved fix has been merged/cherry-picked