soc/intel/cannonlake: skip CPU replacement check on CML

jackadam1981 · jackadam1981 · commit fdee1c6dd34c · 2026-06-01T14:29:11.000+08:00
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -136,6 +136,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	m_cfg->Heci1BarAddress = HECI1_BASE_ADDRESS;
 
 	mainboard_memory_init_params(mupd);
+
+#if CONFIG(SOC_INTEL_COMETLAKE)
+	tconfig->SkipCpuReplacementCheck = 1;
+#endif
 }
 
 __weak void mainboard_memory_init_params(FSPM_UPD *mupd)

Original file line number	Diff line number	Diff line change
`@@ -136,6 +136,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)`
`136`	`136`	`m_cfg->Heci1BarAddress = HECI1_BASE_ADDRESS;`
`137`	`137`
`138`	`138`	`mainboard_memory_init_params(mupd);`
	`139`	`+`
	`140`	`+#if CONFIG(SOC_INTEL_COMETLAKE)`
	`141`	`+ tconfig->SkipCpuReplacementCheck = 1;`
	`142`	`+#endif`
`139`	`143`	`}`
`140`	`144`
`141`	`145`	`__weak void mainboard_memory_init_params(FSPM_UPD *mupd)`