AES-Based Hash Core (Full Hash v1)

A high-performance hardware implementation of a custom Hash algorithm based on the AES S-Box. This project was developed as part of the Hardware and Embedded Security course at the University of Pisa.

📌 Project Overview

This module computes a 64-bit digest from an input message of arbitrary size. It leverages the non-linear properties of the AES S-Box to ensure cryptographic robustness. The architecture follows a synchronous FSMD (Finite State Machine with Datapath) approach, partitioned into four distinct logic blocks for optimal timing and modularity.

Key Features

• Algorithm: Iterative transformation using AES S-Box (LUT-based).
• Handshake: Robust partial handshake protocol (READY_TO_READ, byte_in_valid).
• Architecture: Single-inter-round-pipelined iterative design.
• Verification: Golden reference model in C and automated SystemVerilog testbenches.

🛠 Hardware Architecture

The design is optimized for FPGA implementation and includes:

1. Control Unit: A 5-state FSM managing the synchronization and handshake.
2. Datapath: Integrated XOR logic, circular barrel shifter, and AES S-Box LUT.
3. Internal State: 64-bit register array ($H$) initialized with a specific IV.

📊 Performance & Synthesis Results

The core was synthesized and verified on an Intel Cyclone V FPGA (5CGXFC9D6F27C7) using Quartus Prime.

Metric	Value
Max Frequency ($f_{max}$)	111.15 MHz
Throughput (Steady State)	3.07 Mbps
Area Occupancy	224 ALMs
Efficiency	0.0137 Mbps/ALM
Latency	$288B + 9$ clock cycles

📂 Repository Structure

• /db: SystemVerilog source files (Core logic and S-Box LUT).
• /tb: Testbench files for functional verification.
• /model: Golden reference model implemented in C.
• /modelsim: Simulation scripts and waveform configurations.
• /quartus: Project files, SDC constraints, and synthesis reports.

🚀 How to Run

Functional Simulation

You can run the simulation using ModelSim. A Python script launch_project.py is provided to automate the verification process:

1. Compiles the C Golden Model.
2. Runs the ModelSim simulation.
3. Compares the outputs and reports the matching percentage.

Synthesis

Open the project in Intel Quartus Prime, set full_hash_wrapper.sv as the top-level entity, and run the compilation flow to inspect Timing Analysis (STA) and Resource Utilization.

👥 Authors

• Giorgio Cecchi
• Luca Giannini

📄 License

GPLv3 (GNU General Public License v3.0) - See the LICENSE file for details.