B.Sc. Computer Engineer & MSc Cybersecurity Student at the University of Pisa. Passionate about Hardware Security and Networking.
- Empoli, FI
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AES-SBox-Hash-Core
AES-SBox-Hash-Core PublicSystemVerilog (RTL) AES-based Hash core with FSMD architecture. Features a C golden model for verification and optimization for Intel Cyclone V FPGAs.
SystemVerilog
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iot-intrusion-detection-power-analysis
iot-intrusion-detection-power-analysis PublicBachelor's Thesis | IoT Intrusion Detection via Power Analysis
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Cybersecurity-GRC-Strategy-and-Law
Cybersecurity-GRC-Strategy-and-Law PublicProjects and case studies on Cybersecurity Governance, Risk, Compliance (GRC), and IT Law. Includes strategic awareness plans and regulatory analysis (NIS2, GDPR).
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