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dts: pinctrl: add mspm0gx51x support and common-base G-series pinctrl#86

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dts: pinctrl: add mspm0gx51x support and common-base G-series pinctrl#86
Girinandha-M wants to merge 2 commits into
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linumiz:upstream/ti/mspm0gx51x-pinctrl

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@Girinandha-M

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Add pinctrl for MSPM0G gx51x family (G151x/G351x) and extract
nodes shared across all G-series families into a common file.

286 identical nodes moved to mspm0g-common-pinctrl.dtsi.
129 conflict nodes (same pin, different mux values) remain in
per-family delta files. All mux values cross-checked against
SDK device headers (1664/1664 passed).

Tested on LP_MSPM0G3507 and LP_MSPM0G3519 with GPIO, UART,
CANFD, PWM, ADC, DAC, VREF, and SPI samples.

@ssekar15 ssekar15 self-assigned this Apr 17, 2026
@Girinandha-M Girinandha-M force-pushed the upstream/ti/mspm0gx51x-pinctrl branch from d14eeca to cd24265 Compare April 17, 2026 07:26
Girinandha-M added a commit to linumiz/zephyr that referenced this pull request Apr 17, 2026
Update the pinctrl include for the LP_MSPM0G3519 board. This
points the board to the correct mspm0gx51x-pinctrl.dtsi file for the
g351x silicon.

Depends on: zephyrproject-rtos/hal_ti#86 (adds gx51x pinctrl)

Signed-off-by: Girinandha Manivelpandiyan <girinandha@linumiz.com>
@ssekar15

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@JFMSP based on your PR #83.

@JFMSP

JFMSP commented Apr 21, 2026

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@ssekar15 and @Girinandha-M These devices for mspm0g are not designed to continue to share a commonality in pinctrl long term nor are easily scalable. For maintainability I think it is a better practice to keep the device families separate and allow each file to be determined specifically by that devices pin control information. Adding future MSPM0G devices such as MSPM0G5187 will further complicate the base file and require consistent refactor across all current MSPM0G files

I strongly recommend against the creation of a base file.

@ssekar15

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@ssekar15 and @Girinandha-M These devices for mspm0g are not designed to continue to share a commonality in pinctrl long term nor are easily scalable. For maintainability I think it is a better practice to keep the device families separate and allow each file to be determined specifically by that devices pin control information. Adding future MSPM0G devices such as MSPM0G5187 will further complicate the base file and require consistent refactor across all current MSPM0G files

I strongly recommend against the creation of a base file.

I understand your concern we should avoid a 'one-size-fits-all' file. The logic is the standard programming principle of reusable APIs: if multiple SoCs share identical pinctrl logic, we should centralize to prevent duplication and maintenance errors.
If a future device like the MSPM0G5187 is fundamentally different, it simply wouldn't inherit the base file. if a new set of devices compatible, we create a 'Base V2' for new group.

add pin control support for the MSPM0 gx51x family of devices
including MSPM0G151x and MSPM0G351x.
Add initial pinctrl support for devices like LP_MSPM0G3519.

Signed-off-by: Jackson Farley <j-farley@ti.com>
Signed-off-by: Girinandha Manivelpandiyan <girinandha@linumiz.com>
Extract pin mux nodes shared identically across all MSPM0G
families into a common file.

286 nodes identical across both families moved to common.
129 conflict nodes (same label, different mux values) remain
in per-family delta files.

Tested on LP_MSPM0G3507 and LP_MSPM0G3519:
- GPIO, UART, PWM, CANFD, ADC, DAC, VREF, SPI

Signed-off-by: Girinandha Manivelpandiyan <girinandha@linumiz.com>
@Girinandha-M Girinandha-M force-pushed the upstream/ti/mspm0gx51x-pinctrl branch from cd24265 to d7d3835 Compare April 24, 2026 06:41
Girinandha-M added a commit to linumiz/zephyr that referenced this pull request Apr 24, 2026
Update the pinctrl include for the LP_MSPM0G3519 board. This
points the board to the correct mspm0gx51x-pinctrl.dtsi file for the
g351x silicon.

Depends on: zephyrproject-rtos/hal_ti#86 (adds gx51x pinctrl)

Signed-off-by: Girinandha Manivelpandiyan <girinandha@linumiz.com>
@JFMSP

JFMSP commented May 13, 2026

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@ssekar15 and @Girinandha-M These devices for mspm0g are not designed to continue to share a commonality in pinctrl long term nor are easily scalable. For maintainability I think it is a better practice to keep the device families separate and allow each file to be determined specifically by that devices pin control information. Adding future MSPM0G devices such as MSPM0G5187 will further complicate the base file and require consistent refactor across all current MSPM0G files
I strongly recommend against the creation of a base file.

I understand your concern we should avoid a 'one-size-fits-all' file. The logic is the standard programming principle of reusable APIs: if multiple SoCs share identical pinctrl logic, we should centralize to prevent duplication and maintenance errors. If a future device like the MSPM0G5187 is fundamentally different, it simply wouldn't inherit the base file. if a new set of devices compatible, we create a 'Base V2' for new group.

The worry here for me is that we'll end up having a V3, V4, and so on as additional devices get added, and we can avoid the headache, and the savings from this long term I think will start to be outweighed by the headache of maintaining a common file.

Girinandha-M added a commit to linumiz/zephyr that referenced this pull request May 24, 2026
Update the pinctrl include for the LP_MSPM0G3519 board. This
points the board to the correct mspm0gx51x-pinctrl.dtsi file for the
g351x silicon.

Depends on: zephyrproject-rtos/hal_ti#86 (adds gx51x pinctrl)

Signed-off-by: Girinandha Manivelpandiyan <girinandha@linumiz.com>
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3 participants