AI designed this project based on the AICP protocol, offering a new approach to chip architecture. Experts welcome to dive deeper.
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The ISA is a set of Envelop paths. NVIDIA defines CUDA instructions. Google defines TPU instructions. Both are fixed at silicon design time. AICP's ISA is queryable at runtime. Adding a new instruction means adding a new Envelop path. No hardware redesign. No silicon respin.
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Model compilation is Envelop translation. You send model layers
["Conv2D", "ReLU", "MaxPool"]. The chip replies with["LOAD", "CONV2D", "ACTIVATE", "POOL", "STORE"]. Operator fusion — Conv+ReLU+Pool into a single instruction — is another Envelop translation. The compiler is not a complex optimization framework. It's an Envelop transformer. -
The memory hierarchy is a queryable Envelop response. Register 1KB/1cyc → SRAM 256KB/5cyc → HBM 8GB/50cyc → DDR 32GB/200cyc. Any layer can query memory specs at runtime and make data placement decisions. No hardcoded assumptions about hardware.
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Chiplet interconnect is Envelop forwarding. Sending a tensor from chiplet-1 to chiplet-2 is structurally identical to cross-node RPC in distributed systems. NVLink, CXL — these are just transport layers. The protocol is the same.
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AI generated this from the protocol alone. No CUDA documentation. No TPU architecture papers. No chip design textbooks. The AI read only the AICP protocol and generated a complete 8-core AI accelerator with 4-tier memory hierarchy, compiler with operator fusion, runtime scheduler, power management, and chiplet interconnect.
1. Chip ISAs are frozen at fabrication. A traditional chip's instruction set is fixed in silicon. An AICP chip's ISA is defined by the protocol. Add a new instruction post-fabrication by registering a new Envelop path. This enables software-defined chips.
2. The AI chip design stack is fragmented. ISA design, tensor core layout, memory hierarchy optimization, compiler development — each is a separate engineering domain with separate teams and tools. AICP unifies them under a single message-flow protocol. The same Envelop that queries the ISA also schedules tasks and moves data between memory tiers.
3. Multi-vendor chiplet integration is a nightmare. NVLink is NVIDIA. CXL is Intel. UCIe is an emerging standard. Each is its own physical protocol. AICP defines chiplet communication as Envelop forwarding — any chiplet that implements AICP can talk to any other, regardless of the underlying physical transport.
Open question: Can the entire AI chip design stack really be expressed as a protocol? NVIDIA, Google, and AMD spend years and billions designing fixed-function accelerators. If the ISA is just a set of Envelop paths, what exactly are we paying for — the silicon, or the architecture?
| Project | Description |
|---|---|
| aicp-eat | Core engine / 核心引擎 |
| aicp-os-kernel | Microkernel OS / 微内核操作系统 |
| aicp-quantum | Quantum computing / 量子计算 |
| aicp-protein | Protein folding / 蛋白质折叠 |
| aicp-llm-trainer | LLM training / 大模型训练 |
| aicp-riemann | Riemann Hypothesis / 黎曼猜想 |
| aicp-ai-chip | AI chip design / AI 芯片设计 |
| aicp-raw-experiments | Raw experiments / 原始实验 |
MIT · See LICENSE