fwTPM demo updates: PolarFire SoC, ZCU102 R5, STM32H5

[dgarske]

Three independent fwTPM example updates, one self-contained commit each:

PolarFire SoC fwTPM (Microchip MPFS250T)

• New default DDR_WCB transport: the shared mailbox lives in the non-cached 0xC0000000 DDR window so it is coherent for the bare-metal hart 4 (the U54 L1d is write-back with no cache-maintenance instruction, so a cacheable mailbox is not coherent on the stock HSS).
• hart 4 runs real TPM 2.0 commands itself at startup (TPM2_Startup, TPM2_GetCapability, TPM2_GetRandom); the single fwtpm_caps.py client reads the result over /dev/mem and reports PASS/FAIL.
• Verified end-to-end on the Video Kit: caps (Manufacturer "WOLF") and live System Controller TRNG entropy.

ZCU102 R5 fwTPM (Xilinx)

• fwtpm_caps.c: APU-side TPM2_GetCapability client over OpenAMP rpmsg (the examples/wrap/caps analogue), plus a PetaLinux fwtpm-caps recipe that installs /usr/bin/fwtpm_caps.

STM32H5 fwTPM

• fwtpm_nv_flash.c: append-only NV journal on STM32H5 internal flash, so TPM NV state survives a power cycle. Requires wolfTPM v4.1.0+ (append-only NV HAL, PR #540) — documented in the README and user_settings.h.

Each example's README and the root README are updated.