Register file with one synchronous write port and several independent read ports, modeled in SystemVerilog like a small SRAM. Each read port decodes its own address, so multiple reads and a write complete in the same cycle. Parameterized width, depth and port count, with assertions and Yosys synthesis.
asic fpga verilog systemverilog computer-architecture alu gtkwave vlsi digital-design verilator arithmetic-logic-unit rtl-design yosy parameterized-design
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Updated
Nov 4, 2026