timing-closure

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Fixed-point MAC accelerator designed to study ASIC timing closure, pipelining, and accumulation feedback in Sky130.

End-to-end RTL to GDSII ASIC physical design implementation at 28nm using Synopsys DC and ICC2 with full timing closure and DRC clean signoff.

asic routing synthesis cts placement vlsi-physical-design pnr cmos digitaldesign icc2 floorplanning designcompiler timing-closure rtl-to-gdsii

Pipelined INT8 MAC PE — Full ASIC flow on SKY130 PDK using Yosys, OpenSTA, OpenLane 2

asic gds vlsi drc physical-design openroad timing-closure sky130 openlane2

Useful scripts to run and configure InTime with the Xilinx Vivado tools.

fpga xilinx vivado optimization-tools timing-closure

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