register-file

Synthesizable RV32I RISC-V core in SystemVerilog where fetch, decode, execute, memory access and write-back complete in a single clock cycle, with ALU, register file, immediate generator and control unit.

Hardware designs modelled with verilog

This is an implementation of a simple CPU in Logisim and Verilog.

Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.

A Datapath design which able to execute store operation as memory instruction, substraction and or operations as arithmetic instruction by Logisim. Additional explanations in readme.

Computer Architecture - Practical Solution with Quartus - Sharif University of Technology

Processor VHDL 💾 assignments for module: CSU22022

VHDL register file with generic bitwidth, number of global register, number of windows, and number of registers per window.

bust generates the register file of a register map from a JSON for FPGA or ASIC modules.

8-bit custom MCU built in Logisim Evolution that executes cyclic array rotation using a handcrafted ISA, register file, ALU, control unit, and data memory — fully functional single-cycle processor.

Проектирование микропроцессора по микроархитектуре RISC-V на SystemVerilog + ASM

A simple RISC processor designed in Verilog HDL, demonstrating fundamental CPU architecture concepts such as instruction execution, ALU operations, register files, memory access, and control logic.

Standalone 16-bit ALU + 8x16 register-file datapath in SystemVerilog, with self-checking testbench and Icarus/GTKWave simulation.

4-Bit Register File Designs. This repository features two designs: a minimalist RB1574B using 74HC157 multiplexers for selective reads, and a full RB1534B using 74HC153 multiplexers for complete read/write flexibility. Includes technical details, IC lists and wiring strategies.

A hardware implementation of a MIPS processor written in VHDL

Implementação didática de um processador de 16 bits multiciclo em Logisim, com arquitetura Harvard, 16 registradores, ULA, unidade de controle e memórias separadas para programa e dados.

Verilog implementation of a simple 16-bit CPU with datapath, ALU, register files and instruction execution.

A parameterized Verilog Register File featuring synchronous write, dual asynchronous read ports, configurable data width and memory depth, along with a comprehensive testbench for functional verification.

This is a 16-bit R-type instruction processor with register file, UAL, and instruction memory (RAM). Ideal for learning about processor design, it supports 8 arithmetic and logic operations and provides a starting point for building more complex designs.

Logisim implementation of a custom 22-bit MIPS-like single-cycle datapath with control unit and a Python assembler that outputs Logisim ROM images.