de0

Controle de motor DC + Sensores fim de curso implementado em VHDL para o kit DE0-CV utilizado na matéria de Elementos de sistemas do 3 semestre de Engenharia da computação do Insper.

DE0 FPGA Labs (Terasic DE0, Cyclone III EP3C16F484C6) — collection of practical projects: arbitrary waveform generator (stage 2-3), ultrasonic RF echo envelope extraction with 7 methods + 3-peak detection + Qt GUI (stage 4).

Reaction-time game for the DE0 FPGA board, built with SystemVerilog and Quartus II

Encryption/Decryption unit in FPGA written in VHDL with use of test benches and simulations

Template for VHDL projects (using the DE0 board)

Scrolling marquee for the Altera DE0 board