apb4

Here are 8 public repositories matching this topic...

FLASHICON / amba-apb4-gpio-timer-subsystem

APB4 slave peripheral block in SystemVerilog that puts a GPIO controller and a programmable timer behind one register map. A bus master configures pins and the timer with ordinary read and write transfers, and protocol assertions check every transaction. Simulated with Verilator and GTKWave, synthesized with Yosys.

asic gpio timer verilog systemverilog gtkwave soc vlsi yosys digital-design verilator amba apb amba-apb rtl-design register-map apb4

Updated Nov 4, 2026

Nam24-dot / apb4-axi4-uvm-verification-portfolio

Star

Public portfolio of APB4 and AXI4 verification methodology using SystemVerilog, UVM, SVA and coverage.

coverage systemverilog uvm constrained-random sva axi4 design-verification rtl-verification apb4

Updated Jun 2, 2026

Nam24-dot / Nam24-dot

Star

Design Verification Engineer portfolio: SystemVerilog, UVM, SVA, APB4, AXI4-Lite, coverage, RISC-V and FPGA.

fpga systemverilog uvm risc-v sva axi4 design-verification rtl-verification apb4 verification-engineer

Updated Jun 2, 2026

Kavinsrib / apb4-peripheral

Star

Configurable APB4 peripheral designed and verified using SystemVerilog, with functional verification, protocol assertions, and Yosys synthesis.

systemverilog yosys systemverilog-simulation systemverilog-test-bench systemverilog-assertions apb4

Updated Sep 6, 2026
Verilog

v0r0bb / uart_pl

Star

PL-based UART IP core interfaced with the PS in Zynq 7000 SoC

fifo apb4

Updated May 11, 2026
SystemVerilog

Nam24-dot / apb4-uvm-lab

Star

Runnable APB4 master/slave RTL verification lab with UVM regressions, scoreboards, coverage, SVA and QuestaSim scripts.

coverage regression systemverilog questasim uvm amba sva design-verification rtl-verification apb4

Updated Jun 2, 2026
SystemVerilog

Nam24-dot / systemverilog-sva-protocol-checkers

Star

Reusable SystemVerilog Assertions and self-checking simulation examples for APB4 protocol verification.

assertions systemverilog questasim sva design-verification protocol-verification rtl-verification apb4

Updated Jun 2, 2026
SystemVerilog

vohoangnguyennnn / APB4-ip-framework

Star

AMBA APB4 peripheral framework with reusable protocol logic, register bank, GPIO/Timer examples, and UVM verification.

rtl systemverilog uvm amba-apb apb4

Updated Aug 22, 2026
SystemVerilog

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