plat-qcom: Add BOBCAT architecture/IPQ Platforms support

core/arch/arm/plat-qcom/bobcat/arch_config.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef ARCH_CONFIG_H
+#define ARCH_CONFIG_H
+
+#define IMEM_DIAG_OFFSET		UL(0x730)
+#define DIAG_SIZE			UL(0x6000)
+#define DIAG_BASE			UL(0x8608000)
+#define DIAG_LOG_START_INFO		(IMEM_BASE + IMEM_DIAG_OFFSET)
+#define TCSR_BOOT_MISC_DETECT		UL(0x195C100)
+
+#endif /* ARCH_CONFIG_H */

core/arch/arm/plat-qcom/bobcat/ipq52xx/target.mk

@@ -0,0 +1,8 @@
+$(call force,CFG_TEE_CORE_NB_CORE,4)
+CFG_NUM_THREADS ?= 4
+
+CFG_TZDRAM_START ?= 0x87D80000
+CFG_TZDRAM_SIZE ?= 0x280000
+CFG_TEE_RAM_VA_SIZE ?= 0x280000
+
+CFG_QCOM_DIAG_LOG ?= $(if $(filter y,$(CFG_TEE_CORE_DEBUG)),y,n)

core/arch/arm/plat-qcom/bobcat/ipq52xx/target_config.h

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef TARGET_CONFIG_H
+#define TARGET_CONFIG_H
+
+#define GENI_UART_REG_BASE		UL(0x1A84000)
+
+#define DRAM0_BASE			UL(0x80000000)
+#define DRAM0_SIZE			UL(0x80000000)
+#define DRAM1_BASE			ULL(0x800000000)
+#define DRAM1_SIZE			UL(0x80000000)
+
+#define GICD_BASE			UL(0xB000000)
+#define GICC_BASE			UL(0xB002000)
+#define GICD_PIDR2			UL(0xFD8)
+
+#define IMEM_BASE			UL(0x8600000)
+#define IMEM_SIZE			UL(0x18000)
+
+#endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/bobcat/ipq96xx/target.mk

@@ -0,0 +1,11 @@
+$(call force,CFG_TEE_CORE_NB_CORE,5)
+$(call force,CFG_CORE_CLUSTER_SHIFT,3)
+CFG_NUM_THREADS ?= 5
+
+$(call force,CFG_ARM_GICV3,y)
+
+CFG_TZDRAM_START ?= 0x8A680000
+CFG_TZDRAM_SIZE ?= 0x280000
+CFG_TEE_RAM_VA_SIZE ?= 0x280000
+
+CFG_QCOM_DIAG_LOG ?= $(if $(filter y,$(CFG_TEE_CORE_DEBUG)),y,n)

core/arch/arm/plat-qcom/bobcat/ipq96xx/target_config.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef TARGET_CONFIG_H
+#define TARGET_CONFIG_H
+
+#define GENI_UART_REG_BASE		UL(0x1A98000)
+
+#define DRAM0_BASE			UL(0x80000000)
+#define DRAM0_SIZE			UL(0x80000000)
+#define DRAM1_BASE			ULL(0x800000000)
+#define DRAM1_SIZE			ULL(0x380000000)
+
+#define GICD_BASE			UL(0xF200000)
+#define GICR_BASE			UL(0xF240000)
+
+#define IMEM_BASE			UL(0x8600000)
+#define IMEM_SIZE			UL(0x20000)
+
+#endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/conf.mk

@@ -3,7 +3,6 @@
 PLATFORM_FLAVOR ?= kodiak
 
 $(call force,CFG_GIC,y)
-$(call force,CFG_ARM_GICV3,y)
 $(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
 $(call force,CFG_ARM64_core,y)
 $(call force,CFG_WITH_ARM_TRUSTED_FW,y)
@@ -22,31 +21,18 @@ CFG_QCOM_GENI_UART_RDY_WAIT_USEC ?= 1000
 ta-targets = ta_arm64
 supported-ta-targets ?= ta_arm64
 
-ifneq (,$(filter $(PLATFORM_FLAVOR),kodiak lemans))
-include core/arch/arm/cpu/cortex-armv8-0.mk
-$(call force,CFG_TEE_CORE_NB_CORE,8)
+# Architecture family mapping
+HOYA_ARCH_CHIPSETS := kodiak lemans
+BOBCAT_ARCH_CHIPSETS := ipq96xx ipq52xx
 
-$(call force,CFG_QCOM_RAMBLUR_PIMEM_V3,y)
-CFG_QCOM_RAMBLUR_TA_WINDOW_ID ?= 2
-
-$(call force,CFG_QCOM_PRNG,y)
-
-CFG_TZDRAM_START ?= 0x1c300000
-CFG_TEE_RAM_VA_SIZE ?= 0x200000
-CFG_TA_RAM_VA_SIZE ?= 0x1c00000
-CFG_TZDRAM_SIZE  ?= (CFG_TEE_RAM_VA_SIZE + CFG_TA_RAM_VA_SIZE)
-CFG_NUM_THREADS  ?= 8
-endif
-
-ifneq (,$(filter $(PLATFORM_FLAVOR),kodiak))
-CFG_DRIVERS_CLK ?= y
-CFG_QCOM_PAS_PTA ?= y
-endif
-
-ifeq ($(CFG_QCOM_PAS_PTA),y)
-# Increase late mappings to cover all PAS resources
-CFG_RESERVED_VASPACE_SIZE ?= (60 * 1024 * 1024)
-$(call force,CFG_DRIVERS_QCOM_CLK,y,Mandated by CFG_QCOM_PAS_PTA)
-CFG_IN_TREE_EARLY_TAS += qcom_pas/cff7d191-7ca0-4784-af13-48223b9a4fbe
+ifneq (,$(filter $(PLATFORM_FLAVOR),$(HOYA_ARCH_CHIPSETS)))
+QCOM_ARCH_FAMILY := hoya
+else ifneq (,$(filter $(PLATFORM_FLAVOR),$(BOBCAT_ARCH_CHIPSETS)))
+QCOM_ARCH_FAMILY := bobcat
+else
+$(error Unsupported PLATFORM_FLAVOR: $(PLATFORM_FLAVOR))
 endif
 
+# Include architecture-specific configurations
+-include core/arch/arm/plat-qcom/$(QCOM_ARCH_FAMILY)/arch.mk
+-include core/arch/arm/plat-qcom/$(QCOM_ARCH_FAMILY)/$(PLATFORM_FLAVOR)/target.mk

core/arch/arm/plat-qcom/diag_log.c

@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <io.h>
+#include <kernel/misc.h>
+#include <mm/core_memprot.h>
+#include <mm/core_mmu.h>
+#include <platform_config.h>
+#include <string.h>
+#include <trace.h>
+
+#include "diag_log.h"
+
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, DIAG_BASE, DIAG_SIZE);
+register_phys_mem_pgdir(MEM_AREA_IO_SEC,
+			(DIAG_LOG_START_INFO & ~SMALL_PAGE_MASK),
+			SMALL_PAGE_SIZE);
+register_phys_mem_pgdir(MEM_AREA_IO_SEC,
+			(TCSR_BOOT_MISC_DETECT & ~SMALL_PAGE_MASK),
+			SMALL_PAGE_SIZE);
+
+#define DIAG_VERSION_V1		1
+#define DIAG_MAGIC_INIT		0x47414944
+#define DIAG_MAGIC_FAILED	0xDEADBEEF
+#define DIAG_MAGIC_DLOAD	0xD15AB1ED
+#define DLOAD_MAGIC_COOKIE	0x10
+
+struct diag_hdr {
+	uint32_t version;
+	uint32_t magic;
+};
+
+struct diag_conf {
+	uint32_t buf_offset;
+	uint32_t buf_size;
+};
+
+struct circ_wo_buf {
+	uint32_t wrap;
+	uint32_t head;
+	uint8_t buf[];
+};
+
+struct diag {
+	struct diag_hdr hdr;
+	struct diag_conf conf;
+	struct circ_wo_buf wo_cbuf;
+};
+
+static struct diag *global_diag;
+
+static struct diag *get_diag_region(void)
+{
+	struct diag *diag;
+	uint32_t *tcsr_reg;
+
+	tcsr_reg = phys_to_virt(TCSR_BOOT_MISC_DETECT, MEM_AREA_IO_SEC,
+				sizeof(uint32_t));
+	diag = phys_to_virt(DIAG_BASE, MEM_AREA_IO_SEC, DIAG_SIZE);
+
+	if (!tcsr_reg || !diag) {
+		EMSG("DIAG: Failed to map regions");
+		return NULL;
+	}
+
+	if (io_read32((vaddr_t)tcsr_reg) == DLOAD_MAGIC_COOKIE) {
+		diag->hdr.magic = DIAG_MAGIC_DLOAD;
+		dsb();
+		return NULL;
+	}
+
+	return diag;
+}
+
+void qcom_diag_log_init(void)
+{
+	struct diag *diag;
+	uint32_t *diag_info_addr;
+
+	if (!IS_ENABLED(CFG_QCOM_DIAG_LOG)) {
+		IMSG("DIAG: Feature not available");
+		return;
+	}
+
+	diag = get_diag_region();
+	if (!diag)
+		return;
+
+	memset(diag, 0, DIAG_SIZE);
+
+	diag->hdr.version = DIAG_VERSION_V1;
+	diag->hdr.magic = DIAG_MAGIC_INIT;
+	diag->conf.buf_offset = offsetof(struct diag, wo_cbuf.buf);
+	diag->conf.buf_size = ROUNDDOWN2(DIAG_SIZE - diag->conf.buf_offset, 16);
+
+	if (diag->conf.buf_offset >= DIAG_SIZE || diag->conf.buf_size == 0) {
+		EMSG("DIAG: Invalid buffer configuration (offset=%u, size=%u)",
+		     diag->conf.buf_offset, diag->conf.buf_size);
+		diag->hdr.magic = DIAG_MAGIC_FAILED;
+		return;
+	}
+
+	diag_info_addr = phys_to_virt(DIAG_LOG_START_INFO, MEM_AREA_IO_SEC,
+				      2 * sizeof(uint32_t));
+	if (diag_info_addr) {
+		io_write32((vaddr_t)&diag_info_addr[0], DIAG_BASE);
+		io_write32((vaddr_t)&diag_info_addr[1], DIAG_SIZE);
+	}
+
+	dsb();
+
+	global_diag = diag;
+}
+
+void qcom_diag_log_puts(const char *str)
+{
+	struct diag *diag = global_diag;
+	const char *p;
+
+	if (!diag || !str)
+		return;
+
+	for (p = str; *p; p++) {
+		diag->wo_cbuf.buf[diag->wo_cbuf.head++] = *p;
+		if (diag->wo_cbuf.head >= diag->conf.buf_size) {
+			diag->wo_cbuf.head = 0;
+			if (diag->wo_cbuf.wrap < UINT32_MAX)
+				diag->wo_cbuf.wrap++;
+		}
+	}
+}

core/arch/arm/plat-qcom/diag_log.h

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DIAG_LOG_H
+#define __DIAG_LOG_H
+
+#include <compiler.h>
+#include <config.h>
+#include <platform_config.h>
+#include <util.h>
+
+void qcom_diag_log_init(void);
+void qcom_diag_log_puts(const char *str);
+
+#endif /* __DIAG_LOG_H */

core/arch/arm/plat-qcom/hoya/arch.mk

@@ -0,0 +1,16 @@
+# HOYA architecture configuration
+
+include core/arch/arm/cpu/cortex-armv8-0.mk
+$(call force,CFG_TEE_CORE_NB_CORE,8)
+
+$(call force,CFG_QCOM_RAMBLUR_PIMEM_V3,y)
+CFG_QCOM_RAMBLUR_TA_WINDOW_ID ?= 2
+
+$(call force,CFG_QCOM_PRNG,y)
+$(call force,CFG_ARM_GICV3,y)
+
+CFG_TZDRAM_START ?= 0x1c300000
+CFG_TEE_RAM_VA_SIZE ?= 0x200000
+CFG_TA_RAM_VA_SIZE ?= 0x1c00000
+CFG_TZDRAM_SIZE ?= (CFG_TEE_RAM_VA_SIZE + CFG_TA_RAM_VA_SIZE)
+CFG_NUM_THREADS ?= 8

core/arch/arm/plat-qcom/hoya/arch_config.h

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2024, Linaro Limited
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef ARCH_CONFIG_H
+#define ARCH_CONFIG_H
+
+#define GICD_BASE			UL(0x17a00000)
+#define GICR_BASE			UL(0x17a60000)
+
+#define RAMBLUR_PIMEM_REG_BASE		UL(0x610000)
+#define SEC_PRNG_REG_BASE		UL(0x010D1000)
+
+#define AOP_MSG_RAM_BASE		UL(0x0C300000)
+#define AOP_MSG_RAM_SIZE		UL(0x00100000)
+
+#define RPMH_BASE_ADDR			UL(0x18200000)
+#define RPMH_RSC_SIZE			UL(0x40000)
+
+#define SECURITY_CONTROL_BASE		UL(0x00780000)
+#define SECURITY_CONTROL_SIZE		UL(0x10000)
+
+#define TCSR_MUTEX_BASE			UL(0x01F40000)
+#define TCSR_MUTEX_SIZE			UL(0x40000)
+
+#define IMEM_DIAG_OFFSET		UL(0x720)
+#define DIAG_SIZE			UL(0x3000)
+#define DIAG_BASE			(IMEM_BASE + IMEM_SIZE - DIAG_SIZE)
+#define DIAG_LOG_START_INFO		(IMEM_BASE + IMEM_DIAG_OFFSET)
+#define TCSR_BOOT_MISC_DETECT		UL(0x1FD3000)
+
+#endif /* ARCH_CONFIG_H */

core/arch/arm/plat-qcom/hoya/kodiak/target.mk

@@ -0,0 +1,21 @@
+CFG_DRIVERS_CLK ?= y
+CFG_DRIVERS_QCOM_CLK ?= y
+
+CFG_QCOM_DIAG_LOG ?= $(if $(filter y,$(CFG_TEE_CORE_DEBUG)),y,n)
+
+CFG_QCOM_QFPROM_FUSEPROV ?= $(if $(filter y,$(CFG_INSECURE)),n,y)
+
+_qcom_fuseprov_deps = $(if $(filter y,$(CFG_QCOM_QFPROM_FUSEPROV)),y,n)
+CFG_QCOM_CMD_DB ?= $(_qcom_fuseprov_deps)
+CFG_QCOM_RPMH_CLIENT ?= $(_qcom_fuseprov_deps)
+CFG_QCOM_QFPROM ?= $(_qcom_fuseprov_deps)
+
+CFG_QCOM_PAS_PTA ?= y
+# Kodiak requires MX voltage rail workaround for QFPROM fuse blowing
+$(call force,CFG_QFPROM_MX_RAIL_WA,y)
+
+ifeq ($(CFG_QCOM_PAS_PTA),y)
+# Increase late mappings to cover all PAS resources
+CFG_RESERVED_VASPACE_SIZE ?= (60 * 1024 * 1024)
+CFG_IN_TREE_EARLY_TAS += qcom_pas/cff7d191-7ca0-4784-af13-48223b9a4fbe
+endif