Fix test_lru_cache_insert_large_grid associativity on ROCm wavefront64#5899
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Fix test_lru_cache_insert_large_grid associativity on ROCm wavefront64#5899q10 wants to merge 1 commit into
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Summary:
`test_lru_cache_insert_large_grid` (added by D105282095) hardcodes the LXU
cache associativity as `32`. The split-embeddings LXU cache is set-associative
with associativity == warp size == `DEFAULT_ASSOC` (32 on NVIDIA, 64 on AMD).
On AMD wavefront64 (gfx942 / MI300) `lru_cache_insert_kernel` strides cache
rows by `kWarpSize = 64` and writes `lxu_cache_state` / `lxu_cache_weights` /
`lru_state` for `slot` in `[0, 64)`, indexing past the 32-wide test
allocations -> out-of-bounds -> non-deterministic memory corruption ->
flaky `assertEqual(lru_state != time_stamp, 0)` failures in OSS ROCm CI
(see P2378242263). On NVIDIA (32 == 32) the allocation matches the kernel,
so the test passed.
Fix (test-only; no kernel/production change):
- Size the three cache tensors and assertions by `DEFAULT_ASSOC` instead of
the literal `32`, matching the established pattern in `lxu_cache_test.py`
and `nbit_cache_test.py`, so the allocation width matches the kernel's
`kWarpSize` associativity on both platforms.
- Fix `torch.accelerator.current_accelerator("cuda")` -> `current_accelerator()`
(the string was silently coerced to `check_available=True`; flagged by
ai_diff_reviewer).
- Generalize the docstring's NVIDIA-specific (32) grid math.
Differential Revision: D108540654
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@q10 has exported this pull request. If you are a Meta employee, you can view the originating Diff in D108540654. |
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pytorch#5899) Summary: `test_lru_cache_insert_large_grid` (added by D105282095) hardcodes the LXU cache associativity as `32`. The split-embeddings LXU cache is set-associative with associativity == warp size == `DEFAULT_ASSOC` (32 on NVIDIA, 64 on AMD). On AMD wavefront64 (gfx942 / MI300) `lru_cache_insert_kernel` strides cache rows by `kWarpSize = 64` and writes `lxu_cache_state` / `lxu_cache_weights` / `lru_state` for `slot` in `[0, 64)`, indexing past the 32-wide test allocations -> out-of-bounds -> non-deterministic memory corruption -> flaky `assertEqual(lru_state != time_stamp, 0)` failures in OSS ROCm CI (see P2378242263). On NVIDIA (32 == 32) the allocation matches the kernel, so the test passed. Fix (test-only; no kernel/production change): - Size the three cache tensors and assertions by `DEFAULT_ASSOC` instead of the literal `32`, matching the established pattern in `lxu_cache_test.py` and `nbit_cache_test.py`, so the allocation width matches the kernel's `kWarpSize` associativity on both platforms. - Fix `torch.accelerator.current_accelerator("cuda")` -> `current_accelerator()` (the string was silently coerced to `check_available=True`; flagged by ai_diff_reviewer). - Generalize the docstring's NVIDIA-specific (32) grid math. Reviewed By: henrylhtsang Differential Revision: D108540654
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This pull request has been merged in 5fd50d1. |
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Summary:
test_lru_cache_insert_large_grid(added by D105282095) hardcodes the LXUcache associativity as
32. The split-embeddings LXU cache is set-associativewith associativity == warp size ==
DEFAULT_ASSOC(32 on NVIDIA, 64 on AMD).On AMD wavefront64 (gfx942 / MI300)
lru_cache_insert_kernelstrides cacherows by
kWarpSize = 64and writeslxu_cache_state/lxu_cache_weights/lru_stateforslotin[0, 64), indexing past the 32-wide testallocations -> out-of-bounds -> non-deterministic memory corruption ->
flaky
assertEqual(lru_state != time_stamp, 0)failures in OSS ROCm CI(see P2378242263). On NVIDIA (32 == 32) the allocation matches the kernel,
so the test passed.
Fix (test-only; no kernel/production change):
DEFAULT_ASSOCinstead ofthe literal
32, matching the established pattern inlxu_cache_test.pyand
nbit_cache_test.py, so the allocation width matches the kernel'skWarpSizeassociativity on both platforms.torch.accelerator.current_accelerator("cuda")->current_accelerator()(the string was silently coerced to
check_available=True; flagged byai_diff_reviewer).
Differential Revision: D108540654