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Merged
DiyouS merged 1 commit into from
Jun 6, 2026
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SOCMIPO: Implementation of partial barrier + test #21

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2 changes: 1 addition & 1 deletion config/cachepool.hjson
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Expand Up @@ -12,7 +12,7 @@
data_width: 32,
id_width_in: 6, // fixed for now
id_width_out: 2, // fixed for now
user_width: 17,
user_width: 21,
axi_cdc_enable: false,
sw_rst_enable: true,
axi_isolate_enable: false,
Expand Down
6 changes: 5 additions & 1 deletion hardware/cachepool_peripheral/cachepool_peripheral.sv
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Expand Up @@ -45,7 +45,8 @@ module cachepool_peripheral
output cache_insn_t l1d_insn_o,
output logic l1d_insn_valid_o,
input logic [NumTiles-1:0] l1d_insn_ready_i,
output logic [NumTiles-1:0] l1d_busy_o
output logic [NumTiles-1:0] l1d_busy_o,
output logic [NumTiles-1:0] barrier_participation_mask_o // SOCMIPO
);

cachepool_peripheral_reg2hw_t reg2hw;
Expand Down Expand Up @@ -200,4 +201,7 @@ module cachepool_peripheral
// The hardware barrier is external and always reads `0`.
assign hw2reg.hw_barrier.d = 0;

// write from software
assign barrier_participation_mask_o = reg2hw.hw_barrier_participation_mask.q;

endmodule
13 changes: 13 additions & 0 deletions hardware/cachepool_peripheral/cachepool_peripheral_reg.hjson
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Expand Up @@ -274,6 +274,19 @@
name: "COMMIT",
desc: "Commit the xbar offset configurations."
}]
},
{
name: "HW_BARRIER_PARTICIPATION_MASK",
desc: '''Hardware barrier participation mask register. This register determines the tiles that are
implicated in a barrier. Allows partial barrier implementation.'''
swaccess: "rw",
hwaccess: "hro",
resval: "15",
fields: [{
bits: "3:0",
name: "HW_BARRIER_PARTICIPATION_MASK",
desc: "Hardware barrier participation mask register."
}]
}
]
}
50 changes: 29 additions & 21 deletions hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv
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Expand Up @@ -90,6 +90,10 @@
logic q;
} cachepool_peripheral_reg2hw_xbar_offset_commit_reg_t;

typedef struct packed {
logic [3:0] q;
} cachepool_peripheral_reg2hw_hw_barrier_participation_mask_reg_t;

typedef struct packed {
logic [31:0] d;
} cachepool_peripheral_hw2reg_hw_barrier_reg_t;
Expand All @@ -115,24 +119,25 @@

// Register -> HW type
typedef struct packed {
cachepool_peripheral_reg2hw_hart_select_mreg_t [1:0] hart_select; // [275:256]
cachepool_peripheral_reg2hw_cl_clint_set_reg_t cl_clint_set; // [255:223]
cachepool_peripheral_reg2hw_cl_clint_clear_reg_t cl_clint_clear; // [222:190]
cachepool_peripheral_reg2hw_hw_barrier_reg_t hw_barrier; // [189:158]
cachepool_peripheral_reg2hw_icache_prefetch_enable_reg_t icache_prefetch_enable; // [157:157]
cachepool_peripheral_reg2hw_spatz_status_reg_t spatz_status; // [156:156]
cachepool_peripheral_reg2hw_spatz_cycle_reg_t spatz_cycle; // [155:124]
cachepool_peripheral_reg2hw_cluster_boot_control_reg_t cluster_boot_control; // [123:92]
cachepool_peripheral_reg2hw_cluster_eoc_exit_reg_t cluster_eoc_exit; // [91:88]
cachepool_peripheral_reg2hw_cfg_l1d_spm_reg_t cfg_l1d_spm; // [87:78]
cachepool_peripheral_reg2hw_cfg_l1d_insn_reg_t cfg_l1d_insn; // [77:76]
cachepool_peripheral_reg2hw_cfg_l1d_tile_sel_reg_t cfg_l1d_tile_sel; // [75:44]
cachepool_peripheral_reg2hw_l1d_spm_commit_reg_t l1d_spm_commit; // [43:43]
cachepool_peripheral_reg2hw_l1d_insn_commit_reg_t l1d_insn_commit; // [42:42]
cachepool_peripheral_reg2hw_l1d_private_reg_t l1d_private; // [41:38]
cachepool_peripheral_reg2hw_l1d_addr_reg_t l1d_addr; // [37:6]
cachepool_peripheral_reg2hw_xbar_offset_reg_t xbar_offset; // [5:1]
cachepool_peripheral_reg2hw_xbar_offset_commit_reg_t xbar_offset_commit; // [0:0]
cachepool_peripheral_reg2hw_hart_select_mreg_t [1:0] hart_select; // [279:260]
cachepool_peripheral_reg2hw_cl_clint_set_reg_t cl_clint_set; // [259:227]
cachepool_peripheral_reg2hw_cl_clint_clear_reg_t cl_clint_clear; // [226:194]
cachepool_peripheral_reg2hw_hw_barrier_reg_t hw_barrier; // [193:162]
cachepool_peripheral_reg2hw_icache_prefetch_enable_reg_t icache_prefetch_enable; // [161:161]
cachepool_peripheral_reg2hw_spatz_status_reg_t spatz_status; // [160:160]
cachepool_peripheral_reg2hw_spatz_cycle_reg_t spatz_cycle; // [159:128]
cachepool_peripheral_reg2hw_cluster_boot_control_reg_t cluster_boot_control; // [127:96]
cachepool_peripheral_reg2hw_cluster_eoc_exit_reg_t cluster_eoc_exit; // [95:92]
cachepool_peripheral_reg2hw_cfg_l1d_spm_reg_t cfg_l1d_spm; // [91:82]
cachepool_peripheral_reg2hw_cfg_l1d_insn_reg_t cfg_l1d_insn; // [81:80]
cachepool_peripheral_reg2hw_cfg_l1d_tile_sel_reg_t cfg_l1d_tile_sel; // [79:48]
cachepool_peripheral_reg2hw_l1d_spm_commit_reg_t l1d_spm_commit; // [47:47]
cachepool_peripheral_reg2hw_l1d_insn_commit_reg_t l1d_insn_commit; // [46:46]
cachepool_peripheral_reg2hw_l1d_private_reg_t l1d_private; // [45:42]
cachepool_peripheral_reg2hw_l1d_addr_reg_t l1d_addr; // [41:10]
cachepool_peripheral_reg2hw_xbar_offset_reg_t xbar_offset; // [9:5]
cachepool_peripheral_reg2hw_xbar_offset_commit_reg_t xbar_offset_commit; // [4:4]
cachepool_peripheral_reg2hw_hw_barrier_participation_mask_reg_t hw_barrier_participation_mask; // [3:0]

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Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]

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message:"Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]" location:{path:"hardware/cachepool_peripheral/cachepool_peripheral_reg_pkg.sv" range:{start:{line:140 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
} cachepool_peripheral_reg2hw_t;

// HW -> register type
Expand Down Expand Up @@ -165,6 +170,7 @@
parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_L1D_ADDR_OFFSET = 7'h 44;
parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET = 7'h 48;
parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_OFFSET = 7'h 4c;
parameter logic [BlockAw-1:0] CACHEPOOL_PERIPHERAL_HW_BARRIER_PARTICIPATION_MASK_OFFSET = 7'h 50;

// Reset values for hwext registers and their fields
parameter logic [31:0] CACHEPOOL_PERIPHERAL_CL_CLINT_SET_RESVAL = 32'h 0;
Expand Down Expand Up @@ -194,11 +200,12 @@
CACHEPOOL_PERIPHERAL_L1D_PRIVATE,
CACHEPOOL_PERIPHERAL_L1D_ADDR,
CACHEPOOL_PERIPHERAL_XBAR_OFFSET,
CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT
CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT,
CACHEPOOL_PERIPHERAL_HW_BARRIER_PARTICIPATION_MASK
} cachepool_peripheral_id_e;

// Register width information to check illegal writes
parameter logic [3:0] CACHEPOOL_PERIPHERAL_PERMIT [20] = '{
parameter logic [3:0] CACHEPOOL_PERIPHERAL_PERMIT [21] = '{
4'b 0011, // index[ 0] CACHEPOOL_PERIPHERAL_HART_SELECT_0
4'b 0011, // index[ 1] CACHEPOOL_PERIPHERAL_HART_SELECT_1
4'b 1111, // index[ 2] CACHEPOOL_PERIPHERAL_CL_CLINT_SET
Expand All @@ -218,7 +225,8 @@
4'b 0001, // index[16] CACHEPOOL_PERIPHERAL_L1D_PRIVATE
4'b 1111, // index[17] CACHEPOOL_PERIPHERAL_L1D_ADDR
4'b 0001, // index[18] CACHEPOOL_PERIPHERAL_XBAR_OFFSET
4'b 0001 // index[19] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT
4'b 0001, // index[19] CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT
4'b 0001 // index[20] CACHEPOOL_PERIPHERAL_HW_BARRIER_PARTICIPATION_MASK
};

endpackage
Expand Down
43 changes: 41 additions & 2 deletions hardware/cachepool_peripheral/cachepool_peripheral_reg_top.sv
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Expand Up @@ -122,6 +122,9 @@ module cachepool_peripheral_reg_top #(
logic xbar_offset_commit_qs;
logic xbar_offset_commit_wd;
logic xbar_offset_commit_we;
logic [3:0] hw_barrier_participation_mask_qs;
logic [3:0] hw_barrier_participation_mask_wd;
logic hw_barrier_participation_mask_we;

// Register instances

Expand Down Expand Up @@ -620,9 +623,36 @@ module cachepool_peripheral_reg_top #(
);


// R[hw_barrier_participation_mask]: V(False)

prim_subreg #(
.DW (4),
.SWACCESS("RW"),
.RESVAL (4'hf)
) u_hw_barrier_participation_mask (
.clk_i (clk_i ),
.rst_ni (rst_ni ),

// from register interface
.we (hw_barrier_participation_mask_we),
.wd (hw_barrier_participation_mask_wd),

// from internal hardware
.de (1'b0),
.d ('0 ),

logic [19:0] addr_hit;
// to internal hardware
.qe (),
.q (reg2hw.hw_barrier_participation_mask.q ),

// to register interface (read)
.qs (hw_barrier_participation_mask_qs)
);




logic [20:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == CACHEPOOL_PERIPHERAL_HART_SELECT_0_OFFSET);
Expand All @@ -645,6 +675,7 @@ module cachepool_peripheral_reg_top #(
addr_hit[17] = (reg_addr == CACHEPOOL_PERIPHERAL_L1D_ADDR_OFFSET);
addr_hit[18] = (reg_addr == CACHEPOOL_PERIPHERAL_XBAR_OFFSET_OFFSET);
addr_hit[19] = (reg_addr == CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_OFFSET);
addr_hit[20] = (reg_addr == CACHEPOOL_PERIPHERAL_HW_BARRIER_PARTICIPATION_MASK_OFFSET);
end

assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Expand All @@ -671,7 +702,8 @@ module cachepool_peripheral_reg_top #(
(addr_hit[16] & (|(CACHEPOOL_PERIPHERAL_PERMIT[16] & ~reg_be))) |
(addr_hit[17] & (|(CACHEPOOL_PERIPHERAL_PERMIT[17] & ~reg_be))) |
(addr_hit[18] & (|(CACHEPOOL_PERIPHERAL_PERMIT[18] & ~reg_be))) |
(addr_hit[19] & (|(CACHEPOOL_PERIPHERAL_PERMIT[19] & ~reg_be)))));
(addr_hit[19] & (|(CACHEPOOL_PERIPHERAL_PERMIT[19] & ~reg_be))) |
(addr_hit[20] & (|(CACHEPOOL_PERIPHERAL_PERMIT[20] & ~reg_be)))));
end

assign hart_select_0_we = addr_hit[0] & reg_we & !reg_error;
Expand Down Expand Up @@ -732,6 +764,9 @@ module cachepool_peripheral_reg_top #(
assign xbar_offset_commit_we = addr_hit[19] & reg_we & !reg_error;
assign xbar_offset_commit_wd = reg_wdata[0];

assign hw_barrier_participation_mask_we = addr_hit[20] & reg_we & !reg_error;
assign hw_barrier_participation_mask_wd = reg_wdata[3:0];

// Read data return
always_comb begin
reg_rdata_next = '0;
Expand Down Expand Up @@ -816,6 +851,10 @@ module cachepool_peripheral_reg_top #(
reg_rdata_next[0] = xbar_offset_commit_qs;
end

addr_hit[20]: begin
reg_rdata_next[3:0] = hw_barrier_participation_mask_qs;
end

default: begin
reg_rdata_next = '1;
end
Expand Down
10 changes: 8 additions & 2 deletions hardware/src/cachepool_cluster.sv
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Expand Up @@ -895,10 +895,15 @@
assign tcdm_start_address = (cluster_base_addr_i & TCDMMask);
assign tcdm_end_address = (tcdm_start_address + TCDMSize) & TCDMMask;


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Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]

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message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hardware/src/cachepool_cluster.sv" range:{start:{line:898 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:898 column:1} end:{line:899}} text:"\n"}


logic [NumTiles-1:0] use_barrier;
// TODO: Connect to CSR
assign use_barrier = {NumTiles{1'b1}};
//assign use_barrier = {NumTiles{1'b1}}; // for now all is set to 1
logic [NumTiles-1:0] barrier_participation_mask;
assign use_barrier = barrier_participation_mask;

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Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]

Raw Output:
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hardware/src/cachepool_cluster.sv" range:{start:{line:906 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:906 column:1} end:{line:907}} text:"\n"}

axi_cut #(
.Bypass (0 ),
Expand Down Expand Up @@ -1043,7 +1048,8 @@
.l1d_insn_o (l1d_insn ),
.l1d_insn_valid_o (l1d_insn_valid ),
.l1d_insn_ready_i (l1d_insn_ready ),
.l1d_busy_o (l1d_busy )
.l1d_busy_o (l1d_busy ),
.barrier_participation_mask_o (barrier_participation_mask)
);

endmodule
8 changes: 7 additions & 1 deletion hardware/src/cachepool_cluster_barrier.sv
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Expand Up @@ -31,7 +31,7 @@
output axi_req_t [NrPorts-1:0] axi_mst_req_o,
input axi_rsp_t [NrPorts-1:0] axi_mst_rsp_i,

input logic [NrPorts-1:0] barrier_i,
input logic [NrPorts-1:0] barrier_i, // participation barrier
input addr_t cluster_periph_start_address_i
);

Expand All @@ -45,8 +45,14 @@
// FSM State of the barrier
barrier_state_e [NrPorts-1:0] state_d, state_q;
// the tiles participate in global barrier

// (SOCMIP) PARTICIPATION MASK!
// (SOCMIP) map to hw then control in sw
logic [NrPorts-1:0] barrier_d, barrier_q;

addr_t barrier_participation_mask_addr;
assign barrier_participation_mask_addr = cluster_periph_start_address_i + CACHEPOOL_PERIPHERAL_HW_BARRIER_PARTICIPATION_MASK_OFFSET;

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Line length exceeds max: 100; is: 134 [Style: line-length] [line-length]

Raw Output:
message:"Line length exceeds max: 100; is: 134 [Style: line-length] [line-length]" location:{path:"hardware/src/cachepool_cluster_barrier.sv" range:{start:{line:54 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

// Infomation stored for response generation
typedef struct packed {
axi_id_t id;
Expand Down
14 changes: 14 additions & 0 deletions software/snRuntime/include/cachepool_peripheral.h
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Expand Up @@ -135,6 +135,20 @@ extern "C" {
#define CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_REG_OFFSET 0x4c
#define CACHEPOOL_PERIPHERAL_XBAR_OFFSET_COMMIT_COMMIT_BIT 0

// Hardware barrier participation mask register. This register determines the
// tiles that are
#define CACHEPOOL_PERIPHERAL_HW_BARRIER_PARTICIPATION_MASK_REG_OFFSET 0x50
#define CACHEPOOL_PERIPHERAL_HW_BARRIER_PARTICIPATION_MASK_HW_BARRIER_PARTICIPATION_MASK_MASK \
0xf
#define CACHEPOOL_PERIPHERAL_HW_BARRIER_PARTICIPATION_MASK_HW_BARRIER_PARTICIPATION_MASK_OFFSET \
0
#define CACHEPOOL_PERIPHERAL_HW_BARRIER_PARTICIPATION_MASK_HW_BARRIER_PARTICIPATION_MASK_FIELD \
((bitfield_field32_t){ \
.mask = \
CACHEPOOL_PERIPHERAL_HW_BARRIER_PARTICIPATION_MASK_HW_BARRIER_PARTICIPATION_MASK_MASK, \
.index = \
CACHEPOOL_PERIPHERAL_HW_BARRIER_PARTICIPATION_MASK_HW_BARRIER_PARTICIPATION_MASK_OFFSET})

#ifdef __cplusplus
} // extern "C"
#endif
Expand Down
3 changes: 3 additions & 0 deletions software/snRuntime/include/snrt.h
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Expand Up @@ -95,6 +95,9 @@ extern void snrt_wakeup(uint32_t mask);
/// get pointer to barrier register
extern uint32_t _snrt_barrier_reg_ptr();

/// get pointer to participation barrier register
extern uint32_t _snrt_barrier_participation_mask_reg_ptr();

/// get start address of global memory
extern snrt_slice_t snrt_global_memory();
/// get start address of the cluster's tcdm memory
Expand Down
1 change: 1 addition & 0 deletions software/snRuntime/include/team.h
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Expand Up @@ -41,5 +41,6 @@ struct snrt_team_root {
struct snrt_allocator allocator;
struct snrt_barrier cluster_barrier;
uint32_t barrier_reg_ptr;
uint32_t barrier_participation_mask_reg_ptr; //SOCMIPO
struct snrt_peripherals peripherals;
};
3 changes: 2 additions & 1 deletion software/snRuntime/src/platforms/shared/start.c
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Expand Up @@ -59,7 +59,8 @@ void _snrt_init_team(uint32_t cluster_core_id, uint32_t cluster_core_num,
team->cluster_mem.end = (uint64_t)spm_start + bootdata->tcdm_size;
team->barrier_reg_ptr = (uint32_t)spm_start + bootdata->tcdm_size +
CACHEPOOL_PERIPHERAL_HW_BARRIER_REG_OFFSET;

team->barrier_participation_mask_reg_ptr = (uint32_t)spm_start + bootdata->tcdm_size +
CACHEPOOL_PERIPHERAL_HW_BARRIER_PARTICIPATION_MASK_REG_OFFSET;
// Initialize cluster barrier
team->cluster_barrier.barrier = 0;
team->cluster_barrier.barrier_iteration = 0;
Expand Down
5 changes: 5 additions & 0 deletions software/snRuntime/src/team.c
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Expand Up @@ -108,6 +108,11 @@ uint32_t _snrt_barrier_reg_ptr() {
return _snrt_team_current->root->barrier_reg_ptr;
}

// Socmipo
uint32_t _snrt_barrier_participation_mask_reg_ptr() {
return _snrt_team_current->root->barrier_participation_mask_reg_ptr;
}

snrt_slice_t snrt_global_memory() {
return _snrt_team_current->root->global_mem;
}
Expand Down
4 changes: 4 additions & 0 deletions software/tests/CMakeLists.txt
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Expand Up @@ -53,6 +53,8 @@ macro(add_spatz_test_threeParam name file param1 param2 param3)
endmacro()




# Benchmark library
add_library(benchmark benchmark/benchmark.c)
add_library(spin_lock benchmark/spin_lock.c)
Expand Down Expand Up @@ -84,6 +86,8 @@ set(SNITCH_TEST_PREFIX cachepool-)

## RLC
add_spatz_test_zeroParam(spin-lock spin-lock/main.c)
add_spatz_test_zeroParam(partial_barrier partial_barrier/main.c)# SOCMIPO
add_spatz_test_zeroParam(partial_barrier_benchmark partial_barrier_benchmark/main.c)# SOCMIPO
add_spatz_test_zeroParam(mcs-lock mcs-lock/main.c)
add_spatz_test_zeroParam(byte-enable byte-enable/main.c)
add_spatz_test_zeroParam(cache-line-rw-smoke cache-line-rw-smoke/main.c)
Expand Down
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