NYCU-ICLAB-2024

簡介

• 學校 : 國立陽明交通大學 (NYCU)
• 開課單位 : 電子碩
• 課程名稱 : 積體電路設計實驗 (Integrated Circuit Design Laboratory)
• 授課教授 : 李鎮宜 教授
• 修課時間 : 2024年02月 ~ 2024年06月
• 最終成績 : A (Rank 39/127)

成績

• 原始成績: 83.92
• Pass/Fail Labs (No Performance Ranking): Lab03, Lab10, Lab13, Online Test

項目	Lab01	Lab02	Lab03	Lab04	Lab05	Lab06	Online Test
占比	5%	5%	5%	5%	5%	5%	5%
成績	96.05	99.45	100	82	40	73.94	50
RANK	15	3	-	48	68	62	-

項目	Lab07	Lab08	Lab09	Lab10	Lab11	Lab12	Lab13
占比	5%	5%	5%	3%	5%	5%	5%
成績	97.47	94.84	98.89	100	95.81	86.98	100
RANK	40	15	10	-	12	41	-

項目	Midterm Exam	Midterm Project	Final Exam	Final Project
占比	8%	8%	8%	8%
成績	81	40	95.5	97.91
RANK	35	73	8	5

實驗總覽

Lab	Project Name	Topic / Key Technology
Lab01	Code Calculator	Combinational Circuit Design
Lab02	Enigma Machine	Sequential Circuit Design
Lab03	AXI-SPI DataBridge	Testbench Design & Bus Protocol
Lab04	Convolutional Neural Network	Synopsys DesignWare IP Integration
Lab05	Matrix convolution, max pooling and transposed convolution	Memory Compiler (SRAM Generation)
Lab06	Huffman Code Operation	Logic Synthesis (Custom TCL for Design Compiler)
Lab07	Matrix Multiplication with Clock Domain Crossing	Clock Domain Crossing (CDC) & Verification (JasperGold)
Lab08	Tea House (RTL)	SystemVerilog: RTL Design
Lab09	Tea House (Verification)	SystemVerilog: Verification (SVA)
Lab10	AXI4-Lite bridge	SystemVerilog: Formal Verification (JasperGold)
Lab11	Siamese Neural Network	Low Power Design (Clock Gating) & Power Analysis
Lab12	Matrix Conv. (Lab05)	Physical Implementation (Innovus: RTL to Post-Sim)
Lab13	APR: Huffman Code Operation	Physical Design & Analysis (IR drop / Power)
Online Test	Infix to prefix converter and prefix evaluation	Real-time RTL Design Challenge
Midterm Project	Maze Router Accelerator	SoC Accelerator Design with AXI4 Interface
Final Project	Single-core CPU	Processor Design & Physical Implementation Flow