feat: add SystemVerilog editor assist phase 1

[hkimw]

Summary

• Add a dependency-free stdio JSON-RPC adapter for verible-verilog-ls plus an explicit verible-verilog-lint diagnostics command.
• Add SystemVerilog keyword completions, language configuration, TextMate grammar, static hover facts, and 20 UVM snippets with IEEE page anchors.
• Add a data-only simulation handoff descriptor; no RTL files changed and no language-server binary is bundled.

Standards Evidence

• IEEE 1800-2023 anchors: Clause 5.6 p.74, Annex B Table B.1 pp.1219-1220, Clause 6 p.88, Clause 8 p.179, Clause 13 p.335, Clauses 23-25 pp.728-780.
• IEEE 1800.2-2020 anchors: Clause 8.3 p.75, Clause 9.6 p.92, Clause 12 p.120, Clauses 13.2-13.7 pp.172-175, Clauses 14.1/14.3 pp.177-190, Clause 15.5 p.204, Clauses 18.4-18.5 pp.273-291, Clause 19.1 p.347.
• UVM 1.2 guide anchor: transaction-level component material, pp.32-35.

Validation

• bash scripts/vscode-adapter-smoke.sh
• python3 -m pytest -q
• Local Verible probe: verible-verilog-lint on a temporary SystemVerilog file returned 0 diagnostics with shell: false.

Review Gate

Merge only after code review. This PR is client-side editor assist only and keeps simulation execution behind the existing local validation boundary.