feat(dma): model cycle-driven OAM transfers on the bus

[pakitovic]

Summary

• model DMG OAM DMA as a shared T-cycle transfer with a typed transfer contract, explicit 2-T-cycle startup seam, published bus-impact state, and lifecycle/status views that do not depend on FF46 readback
• route OAM DMA byte movement through the shared machine bus and arbitration path, feed live DMA constraints into CPU and bus arbitration, and extend DMA and bus scheduler traces with the published transfer and arbitration metadata
• add focused DMA unit and integration coverage for startup timing, HRAM-only restriction onset, partial-progress observability, completion ordering, copied OAM contents, shared trace visibility, and arbitration precedence
• update the DMA handbook, testing guidance, and roadmap status/phase notes to document the startup seam, restriction timing, SameBoy timing cross-check, and Phase 3.5 closure
• add extra regression coverage for APU register readback/trigger behavior, serial startup and trace reporting, and cartridge size-decoder and header parsing edge cases

Validation

• make check