feat(core): complete phase 2 temporal cpu baseline

[pakitovic]

Summary

• close the Phase 2 CPU/timer/IRQ/boot baseline on the shared T-cycle scheduler
• add phase-aligned tracing for CPU bus activity, IF visibility, interrupt acceptance, and FF50 handoff
• add focused integration coverage plus typed Phase 2 ROM automation targets in gb-test-runner
• update roadmap and hardware docs, keeping the remaining Phase 2 TODOs explicit

Validation

• cargo test -q
• pre-push checks passed (cargo fmt --all --check, lint, tests, typos, cargo deny)

Remaining explicit TODOs

• full production DMG boot ROM opcode coverage beyond the synthetic Phase 2.4 baseline
• explicit EI ; HALT pending-IRQ verification/refinement
• exact same-cycle TIMA/TMA arbitration on the timer reload T-cycle