[dv] Enable DRAM backdoor for the UVM TB#615
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Add hw/top_chip/dv/common/ as a shared home for simulation-only modules used by both UVM and Verilator. Move sim_sram_axi/ there, move and rename dram_wrapper_sim -> sim_dram_wrapper for naming consistency, and add a FuseSoC core file for the DRAM wrapper. Update top_chip_sim.core and top_chip_verilator.core to depend on the new cores rather than referencing the files directly. Signed-off-by: martin-velay <mvelay@lowrisc.org>
- Add ChipMemDRAM to chip_mem_e - Instantiate the DRAM mem_bkdr_util in tb.sv - Add zero-init DRAM with a direct SV loop before loading the vmem to prevent X values from uninitialised addresses propagating into the tag-controller FIFO (DataKnown_A). - Extend mem_bkdr_write8/read8 in base_vseq to support ChipMemDRAM. Signed-off-by: martin-velay <mvelay@lowrisc.org>
- Update all 33 tests in top_chip_sim_cfg.hjson to pass ChipMemDRAM_image_file and use DRAM-linked vmem files instead of the SRAM-linked _sram variants. - Remove the cmake if(TRUE) block that built _sram binaries solely for UVM. Remove stale _sram reference from dev_guide. Signed-off-by: martin-velay <mvelay@lowrisc.org>
SW symbols are now in the DRAM-linked binary; pass ChipMemDRAM explicitly instead of relying on the ChipMemSRAM default. Signed-off-by: martin-velay <mvelay@lowrisc.org>
Signed-off-by: martin-velay <mvelay@lowrisc.org>
engdoreis
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Jun 18, 2026
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The SW and build system side LGTM, I also tested the UVM test.
[ legend ]: [S: scheduled, Q: queued, R: running, P: passed, F: failed, K: killed, T: total]
00:03:19 [ build ]: [S: 00, Q: 00, R: 00, P: 01, F: 00, K: 00, T: 01] 100%
00:07:43 [ run ]: [S: 00, Q: 00, R: 00, P: 28, F: 04, K: 00, T: 32] 100%
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@engdoreis, good point, also the Gives: |
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This PR addresses issue #514