[rtl] Debug module integration#614
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This includes vendoring the debug module in and including it in the chip top. The CVA6 halt and exception addresses are fed in through the top and the debug module address is fed into the debug module. It also marks the license as Solderpad license for the Pulp debug module. Co-authored-by: Alexandre Joannou <alexandre@capabilitieslimited.co.uk> Co-authored-by: Jonathan Woodruff <jonathan.woodruff@capabilitieslimited.co.uk> Co-authored-by: Ray Lau <ray.lau@lowrisc.org> Co-authored-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
The Verilator config allows program buffer access as fallback Disable GDB hardware breakpoints since these are not supported by the current CVA6 configuration and the trigger_module.sv doesn't work out of the box when enabled. This issue is tracked here: Capabilities-Limited/cheri-cva6#80 Co-authored-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
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With 2 hosts on the primary AXI crossbar, the device-side ID needs to be 1 bit ($clog2(AxiXbarHosts)) wider than the host-side ID. This commit adds device-side AXI types and improves comments about AXI ID widths in top_pkg.sv.
The debug module top now track pending resets and only acknowledges the reset when the core is ready to fetch again.
This is so the debug module knows when the CVA6 is ready to start fetching again.
This only works when SPI device is disconnected.
Before this you could not pass an SramInitFile into the core file.
This adds a shell script that launches Verilator, OpenOCD and GDB. GDB is run through an expect script.
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Marked this pull request as ready for review again because both the FPGA tests are passing and the expect GDB script seems to pass as well. |
raylau1
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| // Virtual jtag | ||
| jtagdpi #( | ||
| .Name("jtag0"), | ||
| .ListenPort(44853) | ||
| ) u_jtagdpi ( | ||
| .clk_i, | ||
| .rst_ni, | ||
| .active(1'b1), | ||
| .jtag_tck(jtag_tck), | ||
| .jtag_tms(jtag_tms), | ||
| .jtag_tdi(jtag_tdi), | ||
| .jtag_tdo(jtag_tdo), | ||
| .jtag_trst_n(jtag_trst_n), | ||
| .jtag_srst_n( ) | ||
| ); | ||
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| lint_off -rule BLKSEQ -file "*/lowrisc_dv_dpi_sv_jtagdpi*/jtagdpi.sv" -match "*ctx = jtagdpi_create(Name, port, assert_srst)*" | ||
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Contributor
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Better to add a comment here:
// Mute RTL style warning from lowRISC JTAG DPI
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| dmi_jtag i_dmi_jtag ( | ||
| .clk_i ( clkmgr_clocks.clk_main_infra ), | ||
| .rst_ni ( rstmgr_resets.rst_debug_n[rstmgr_pkg::DomainMainSel] ), | ||
| .testmode_i ( 1'b0 ), | ||
| .test_rst_ni ( 1'b1 ), | ||
| .dmi_rst_no ( ), // keep open | ||
| .dmi_req_valid_o ( debug_req_valid ), | ||
| .dmi_req_ready_i ( debug_req_ready ), | ||
| .dmi_req_o ( debug_req ), | ||
| .dmi_resp_valid_i( debug_resp_valid), | ||
| .dmi_resp_ready_o( debug_resp_ready), | ||
| .dmi_resp_i ( debug_resp ), | ||
| .tck_i ( dm_jtag_tck ), | ||
| .tms_i ( dm_jtag_tms ), | ||
| .trst_ni ( dm_jtag_trst_n ), | ||
| .td_i ( dm_jtag_tdi ), | ||
| .td_o ( dm_jtag_tdo ), | ||
| .tdo_oe_o ( ) | ||
| ); |
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Nit: port formatting, instance name should be u_dmi_jtag.
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| dmi_jtag i_dmi_jtag ( | ||
| dmi_jtag #( | ||
| .IdcodeValue(jtag_id_pkg::RV_DM_JTAG_IDCODE) | ||
| ) i_dmi_jtag ( |
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| localparam logic [10:0] JEDEC_MANUFACTURER_ID = {4'd12, 7'b110_1111}; | ||
| localparam logic [3:0] JTAG_VERSION = 4'h1; |
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Nit: alignment can be better
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This integrates the debug module into Mocha. It is testable out of the box with Verilator and the JTAG DPI, but on FPGA you must generate a new bitstream. For convenience I have attached a bitstream for those that want to test on FPGA.
mocha_debug_module_spi_disabled.zip
Closes: #303