Update downstream backported patches for TPM GPIO locking

[tlaurion]

Skylake+ and possibly other platforms (t480*)

From discussion on coreboot matrix thread

Turns out the PCH-H datasheets are just wrong and the pad_cfg_lock_offset value for GPIO community 0 was wrong. I fixed it to match edk2-platforms and the Linux pin-ctrl driver and locking seems to be working with my original patch, though with the SBI method instead of the PCR method: https://review.coreboot.org/c/coreboot/+/90885
I will push some patches later
Locking them in SMM as is done in the patch train of https://review.coreboot.org/c/coreboot/+/95545 does not appear to be working on Skylake even with the corrected offsets.

AlderLake

Also patchtrain for alderlake (nv4x_adl), would needs backporting https://review.coreboot.org/q/topic:%22tpm_gpio_pltrst_lock%22 to be applied downstream until next release of Dasahro+Heads

Referred from Dasharo/coreboot#959 (comment)

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TODO

• update downstream forks used patchtrains
• test against nv4xadl
• update https://github.com/tlaurion/tpm-gpio-fail
• update docs

[tlaurion]

Also patchset for alder lake landed (nv4x_adl), would need backporting https://review.coreboot.org/q/topic:%22tpm_gpio_pltrst_lock%22

Referred from Dasharo/coreboot#959 (comment)