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kowsyap/README.md

Kowsyap Pranay Kumar Musumuri

Typing SVG

🧑‍💻 About Me

I'm a Computer Engineering MS student at George Mason University (GPA: 3.89/4.0), specializing in FPGA-based hardware design, RTL design, and hardware-software co-design. My research focuses on implementing post-quantum cryptography in hardware, targeting Xilinx Artix-7 and Zynq SoC platforms.

Previously a Digital Design Engineer at Infosys, designing RTL modules and FPGA-based hardware accelerators. I hold a B.Tech in Electronics Engineering from IIIT Design & Manufacturing Kancheepuram.

🔬 Research   : Post-Quantum Cryptography (MAYO) on FPGA
👨‍🏫 Teaching   : Computer Architecture · Computer Organization · Digital System Design
🎯 Seeking    : Hardware / FPGA / Embedded / RTL Engineering roles (2025/2026)
📍 Location   : Fairfax, VA, USA

🔭 What I'm Up To

🎓 MS Computer Engineering @ George Mason University  GPA: 3.89/4.0
🔬 Research: FPGA implementation of Post-Quantum Cryptography — MAYO Signature Scheme on Xilinx Artix-7 & Zynq Z7-10
👨‍🏫 GTA: Computer Architecture · Computer Organization · Digital System Design (~150 students)
📫 Open to: Hardware / FPGA / Embedded / RTL Engineering roles 2025/2026

🛠️ Tech Stack

⚡ Hardware Description Languages
🔧 EDA & FPGA Tools
💻 Programming Languages
🤖 ML & Data Science
🌐 Web & Cloud

🔬 Featured Projects

🚀 Project 🧰 Stack
🔒 Reconfigurable HW Accelerator for MAYO (Post-Quantum)
FPGA implementation targeting Kintex-7 & Artix-7
HW-SW Co-Design of MAYO Verification on Zynq Z7-10
AES-CTR/SHAKE-256 on PS + DMA AXI-Stream PL accelerators
Tree-Based CMOS Decoder Decomposition for SRAM
14.5% delay improvement for 64x64 SRAM on 180nm tech
Memory-Level Design & UVM Verification of Multi-Port SRAM
Assertions, functional coverage & code coverage reports
Transformer Anomaly Detection
Real-time voltage & temperature monitoring with ML
GenAI-Powered Global Climate Intelligence Dashboard
RAG pipeline with vector memory & LLM-driven insights
ng-dyno-form — Angular Dynamic Forms Library
Dynamic reactive forms with validation & conditional fields
Neuromorphic Motion Detection
Low-power real-time detection using Spiking Neural Networks
8-bit Harvard Architecture Processor
32 registers, 8-bit ALU, 256-location data memory

📄 Publications

📰 Correctness of Synthesis for Tree based Decomposed Algorithm in Semiconductor Memory Designs with Larger Decoders IEEE 2021

🏅 Certifications

📊 GitHub Stats

GitHub Stats    Most Used Languages
GitHub Streak   

⚔️ LeetCode

LeetCode Stats

⚡ "Building the future of secure hardware, one gate at a time." ⚡

Pinned Loading

  1. Physical-Design-and-Verification-of-DPRAM-using-SV-UVM-and-Semi-Custom-Design Physical-Design-and-Verification-of-DPRAM-using-SV-UVM-and-Semi-Custom-Design Public

    Memory Level Verification of Dual Port RAM using SystemVerilog and Universal Verification Methodology Environments with assertions,functional coverage and code coverage report

    JavaScript 29 12

  2. 8-bit-harvard-processor 8-bit-harvard-processor Public

    verilog hdl design of a 8 bit harvard processor

    Verilog 4 1

  3. verilog-projects verilog-projects Public

    verilog hdl codes of various algorithms and circuits

    Verilog 7 1

  4. Smart-Agricultural-System-Based-on-IoT Smart-Agricultural-System-Based-on-IoT Public

    Python 11 4

  5. ng-dyno-form ng-dyno-form Public

    ng-dyno-form is an angular library that helps in creating reactive forms dynamically in easier way

    JavaScript 2

  6. climate-analyst climate-analyst Public

    Global Climate Intelligence Dashboard

    JavaScript 2 1