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  • Joined Jun 7, 2026

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  1. jawadsa02 jawadsa02 Public

    Electrical Engineering portfolio — RTL, VLSI, analog design

  2. dlx-fpga-resa-bringup dlx-fpga-resa-bringup Public

    DLX microprocessor bring-up on Artix-7 — Verilog RTL, Vivado migration, HW-SW co-design

    SMT

  3. sync-fifo-verified sync-fifo-verified Public

    Synchronous FIFO — simulated, formally proven (SymbiYosys), synthesis-gated

    Verilog

  4. uart-buffered-subsystem uart-buffered-subsystem Public

    FIFO-buffered UART subsystem — composes verified uart_tx, uart_rx, and sync_fifo blocks

    Verilog

  5. alu-vlsi-gpdk45 alu-vlsi-gpdk45 Public

    Full-custom ALU in Cadence Virtuoso (gpdk45) — Knowles adder, DRC/LVS clean

  6. ota-analog-design ota-analog-design Public

    OTA design meeting 7 simultaneous specs — Analog Electronic Circuits