Harvard Architecture, Circuits, and Compilers

DreamRAM: A Fine-Grained Configurable Design Space Modeling Tool for Custom 3D Die-Stacked DRAM

FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks

CASCADE - A Composable Analytical System of Chiplets for AI Devices at the Edge -- Democratizing Customization for ML at the Edge through Hetero-Chiplet SiP Architectures

HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference

A pre-RTL, power-performance model for fixed-function accelerators

SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin

End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.

http://vlsiarch.eecs.harvard.edu/research/recommendation/

Documentation for SMAUG. Autogenerated, do not manually edit.