hjpoly.sv-workshop

A collection of reusable SystemVerilog verification utilities and design patterns for ASIC/FPGA development.

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📚 Projects Overview

1. clock_gate_checker

Reusable Clock Gating Verification Interface

A SystemVerilog interface for monitoring and validating clock gating behavior in digital designs. Detects illegal clock transitions when gate controls indicate clocks should be disabled.

Key Features:

• ✅ Enum-based clock domain management with type safety
• ✅ Multi-clock concurrent monitoring using associative arrays
• ✅ Event-driven control (start/disable/terminate per clock)
• ✅ Automatic final report generation with pass/fail status
• ✅ Configurable skip delays for clock tree propagation
• ✅ Non-intrusive passive monitoring

Use Cases:

• Verify clock gating logic doesn't produce glitches
• Monitor multiple clock domains in SoC designs
• Validate low-power clock gating implementations
• Regression testing for clock control bugs

Example:

clock_gate_checker checker();
assign checker.clk[FUNC_CLK] = gated_clock_output;
assign checker.clk_gate[FUNC_CLK] = gate_enable;
checker.start_clock_check(FUNC_CLK);

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2. constraint_trials

SystemVerilog Constraint Operator Precedence Analysis

Experimental testbench investigating SystemVerilog constraint solver behavior with ternary operators and equality operations. Documents IEEE 1800 LRM-compliant operator precedence rules.

Key Features:

• ✅ Tests 4 different constraint syntax variations
• ✅ Separate variable sets for concurrent testing
• ✅ Validated across multiple VCS versions (V-2023.12, X-2025.06)
• ✅ Comprehensive analysis document with LRM references
• ✅ Demonstrates correct vs. problematic syntax patterns

Syntax Variations Tested:

1. a == b ? c : d - Ambiguous precedence (fails)
2. a == (b) ? c : d - Parenthesized condition (fails)
3. a == (b ? c : d) - Explicit ternary grouping (works)
4. if (b) a == c; else a == d - Standard if-else (works)

Key Finding:
The equality operator == has higher precedence than conditional ? : per IEEE 1800 Table 11-2. Expression a == b ? c : d parses as (a == b) ? c : d, not a == (b ? c : d).

Recommended Practices:

• Always use explicit parentheses: a == (b ? c : d)
• Prefer if-else form for clarity: if (b) a == c; else a == d;
• Use implication operator: b -> (a == c)

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3. mem_intf_check

SRAM Interface Verification Checkers

Comprehensive memory interface monitors for validating SRAM read/write operations, ECC behavior, and protocol compliance.

Components:

A. DPRAM Checker (dpram_intf_checker.sv)

Dual-port RAM interface validator with independent read/write port monitoring.

Features:

• Shadow memory for read data verification
• X/Z detection on control signals (addr, we, re, wdata)
• ECC error monitoring (correctable/uncorrectable)
• Independent port A and port B checking
• Configurable read latency (1-N cycles)
• Warning/error severity promotion

B. SPRAM Checker (spram_intf_checker.sv)

Single-port RAM interface validator for shared read/write port designs.

Features:

• Shadow memory with write-through behavior
• Protocol violation detection
• ECC monitoring and reporting
• Configurable latency modeling
• Read-during-write hazard detection

Use Cases:

• Validate memory controller implementations
• Check SRAM wrapper compliance
• Debug read/write timing issues
• Verify ECC logic integration
• Monitor memory arbitration

Example:

dpram_intf_checker #(
  .ADDR_WIDTH(10),
  .DATA_WIDTH(32),
  .READ_LATENCY(2)
) mem_checker();

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4. user_data_from_file

File-Based Stimulus Generation for Testbenches

Utilities for converting text files to hex stimulus and processing data through designs, enabling realistic data-driven verification.

Workflow:

1. Convert text to hex using Unix od command
2. Read hex files as byte streams in SystemVerilog
3. Process data through design under test (DUT)
4. Write output to hex file
5. Convert hex back to text for verification

Key Features:

• ✅ Supports 4-byte and 8-byte hex formats (-An -tx4, -An -tx8)
• ✅ Memory-efficient streaming (configurable chunk sizes)
• ✅ Byte array manipulation utilities (concat, resize, display)
• ✅ ASCII and hex output formatting
• ✅ Complete end-to-end example with DUT

Use Cases:

• Test protocol parsers with real packet data
• Verify compression/decompression engines
• Validate cryptographic blocks with test vectors
• Process image data through video pipelines
• Feed realistic datasets to DUTs

Example Usage:

# Convert text to hex
od -An -tx4 data.txt > data.txt.hex

# Run simulation (reads hex, processes, writes output)
make run

# Convert output back to text
xxd -r -p data.txt.hex.out > output.txt

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🛠️ Build System

All projects use a common Makefile-based build system with Synopsys VCS.

Quick Start

cd <project>/run
make comp    # Compile design and testbench
make run     # Execute simulation
make clean   # Remove build artifacts

Tool Versions

• VCS: T-2022.06-SP2-6 (default), tested with V-2023.12-SP2-7 and X-2025.06-SP2
• Verdi: Integrated waveform debugging with KDB
• Features: UVM support, GUI mode, coverage collection

Adding New Projects

make setup DIR=new_project_name

Creates scaffold with:

• rtl/ - RTL source directory
• tb/ - Testbench directory
• run/ - Simulation directory with Makefile

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📝 Contributing

This is a personal learning and experimentation repository. Feel free to:

• Use these utilities in your projects
• Report issues or suggest improvements
• Fork and extend for your needs

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📧 Contact

Author: Hani John Poly
Repository: https://github.com/hanijohn/hjpoly.sv-workshop