Add copper query and net tie authoring tools for PCB routing

[ecto]

Summary

Adds three new MCP tools for PCB copper inspection and net tie management, completing the read/write algebra for routed copper and intentional net junctions.

Key Changes

• get_copper tool — Query the board's routed copper (traces, trace arcs, vias, zones) with optional filters by layer, net, bounding box, and kind. Returns each element with its index (compatible with delete tools) and geometry, enabling surgical edits without exporting the document. Supports pagination with offset/limit (capped at 200 elements per page).

• add_net_tie tool — Declare intentional junctions between two or more nets (e.g., wye motor neutral points, split-ground stitches, current-sense shunt taps). Supports both board-wide ties and region-scoped ties (position + radius). Validates that all nets exist on the board and rejects half-scoped regions (position without radius or vice versa).

• delete_net_tie tool — Remove a net tie by index, by matching net set (order-insensitive), or by position (±0.001 mm tolerance). Supports guards: passing nets or position alongside index confirms the indexed tie matches before deletion.

• Net tie diffing — Extended PcbElementChange to include "netTie" kind and updated diffPcbElements to track tie mutations in the changed diff (ties report their joined nets as "A+B+C" since they have no single net).

• Copper element bounding boxes — Added copperElementBbox helper to compute conservative axis-aligned bounds for traces, trace arcs, vias, and zones (full-circle bound for arcs to avoid missing copper on bbox queries).

• Via layer spanning — Added viaSpansLayer to check if a via's barrel spans a given copper layer (e.g., a through via FCu→BCu carries In1Cu).

• Schema and validation — Added JSON schemas for all three tools with comprehensive property descriptions. Validation includes layer name normalization, net existence checks, and bbox geometry validation.

• Test coverage — Added comprehensive tests for get_copper (filtering, pagination, index-driven deletes), add_net_tie (board-wide and region-scoped ties, validation), and delete_net_tie (index/net/position matching, guards, DRC integration). Includes an end-to-end test showing that a region-scoped tie exempts a junction short in DRC, and deleting it re-arms the violation.

• Server integration — Registered all three tools in the MCP server, marked add_net_tie and delete_net_tie as document writers (they mutate the session and must persist/be undoable), and updated the PCB workflow blurb in the server instructions.

Implementation Details

• Copper queries iterate collections in deterministic order (traces, arcs, vias, zones; index order within each) to ensure offset-paging never skips or repeats elements.
• Zone outlines can run to hundreds of vertices on dense boards; get_copper reports bbox + vertex count instead of the full outline to keep responses bounded.
• Net ties are DRC data (not copper geometry) but change what run_drc accepts, so they must persist and be undoable like other mutations.
• Tie positions are rounded to 0.001 mm on write; delete_net_tie position matching uses the same ±0.001 mm tolerance, so echoing a position from add_net_tie's result always matches.
• add_net_tie fails closed on a half-scoped region: the kernel's NetTieGroups only forms a region when both position and radius are present, so passing one without the other would silently degrade to a board-wide exemption.

https://claude.ai/code/session_0149H9KjqeyjkVWEihNjMvJS

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Project	Deployment	Actions	Updated (UTC)
vcad-mcp	Building	Preview, Comment	Jul 7, 2026 2:11pm

3 Skipped Deployments

Project	Deployment	Actions	Updated (UTC)
mecheval	Ignored		Jul 7, 2026 2:11pm
vcad	Ignored		Jul 7, 2026 2:11pm
vcad-docs	Ignored		Jul 7, 2026 2:11pm

[chojiai]

What shipped

Three new tools are available for PCB work in this release.

• You can now inspect all routed copper on a board — traces, vias, and poured zones — filtered by layer, net, area, or type, without exporting the full document. Each result includes the exact identifier needed to delete that element directly.
• You can declare intentional connections between two or more nets (for example, a motor's star-point neutral, a split ground, or a current-sense shunt) so the design-rule checker recognizes them as deliberate rather than flagging them as shorts. Scoping a tie to a specific location keeps the checker strict everywhere else on the board.
• You can remove a declared net tie by index, by the nets it joins, or by its position, restoring the short violation if the copper is still there.

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