Remove 128-bit limit on Vector<T> size for ARM64#129852
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If InstructionSet_VectorT is available, set the class instance size to the process SVE vector length. Increase the maximum bound in structMightRepresentSIMDType to allow the JIT to detect this when the ISA is present.
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| #ifdef FEATURE_SIMD | ||
| return (structSize >= getMinVectorByteLength()) && (structSize <= getMaxVectorByteLength()); | ||
| #ifdef TARGET_ARM64 | ||
| const uint32_t max = compExactlyDependsOn(InstructionSet_VectorT) ? MAX_SVE_REGSIZE_BYTES : FP_REGSIZE_BYTES; |
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This is going to potentially cause light up for a lot of unintended structs, which can hurt startup perf
Won't SVE, in most scenarios, rather be "size unknown" and in isolated scenarios a JIT (but not AOT or pre-JIT) environment may be able to explicitly query the true size and optimize a few things (like frame layout)
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Yes agreed, we could query the actual size here in JIT mode, and use this as the upper bound. We can also filter sizes that are powers of 2 in bits, which could help with AOT as well.
As I've added the primitive for it, I could just do this in this PR.
| if (CPUCompileFlags.IsSet(InstructionSet_VectorT)) | ||
| { | ||
| numInstanceFieldBytes = (uint32_t) GetSveLengthFromOS(); | ||
| } |
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This is "correct" because we'll rather have InstructionSet_VectorT128 if we have AdvSimd without SVE, correct?
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Yes, I was thinking it's going to be InstructionSet_VectorT128 XOR InstructionSet_VectorT, never both enabled at the same time. So InstructionSet_VectorT is only serviced by SVE and will not be available when SVE is not there.
At some point we will need to decide if we prefer AdvSimd or SVE when the VL == 128 bits. This is dependent on micro-architecture, but we can find a different reason to pick one generally.
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never both enabled at the same time.
Correct, that should generally be an error scenario and effectively a bug in the ISA detection logic in the VM, but I wanted to make sure it was being persisted here and wasn't something "unique" for the scalable scenario.
At some point we will need to decide if we prefer AdvSimd or SVE when the VL == 128 bits. This is dependent on micro-architecture, but we can find a different reason to pick one generally.
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If
InstructionSet_VectorTis available, set the class instance size to the process SVE vector length.Increase the maximum bound in
structMightRepresentSIMDTypeto allow the JIT to detect this when the ISA is present.