feat(riscv64): RV64A atomic inline-asm mnemonics (lr/sc, amo*, ordering suffixes)#1669
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Extend the riscv64 inline-asm assembler with the A-extension subset that std's riscv64 atomic arms need: lr.w/lr.d, sc.w/sc.d, the amo* read- modify-writes (swap/add/and/or/xor/max/min/maxu/minu) in .w and .d, the .aq/.rl/.aqrl ordering suffixes, and pause for spin_hint. The AMO major opcode (0x2F) is R-type with funct5 in bits [31:27] and the aq/rl bits in [26:25], so the assembled funct7 is (funct5 << 2) | (aq << 1) | rl. Atomics take the base-only (rs1) address form with no displacement, unlike regular loads and stores. lr is the two-operand rd, (rs1) form; sc and the amo* forms are rd, rs2, (rs1). The suffixes are parsed inline so a future rv32 reuses the .w forms. A byte-test covers every mnemonic and ordering variant against llvm-mc -mattr=+a, plus the no-displacement and unsupported-prefix rejections. Part of #1668.
…nalyzer The inline-asm clobber analyzer drove the new atomic mnemonics to the conservative all-register fallback. Classify them precisely: lr / sc / amo* each write their rd operand (the leftmost register), and pause writes nothing like fence. A prefix test (lr. / sc. / amo) covers the whole family across its width and ordering suffixes, so the allocator no longer over-preserves around an atomic block. Extends the clobber test. Part of #1668.
Extend the freestanding rv64 fixture with the RV64A atomics: an lr.d/sc.d compare-and-swap loop swaps a stack cell 0 -> 7 (the reservation-retry and mismatch arms are encoded though the fast path takes neither), then amoadd.d adds 4 and returns the swapped value. the folded result (prior 7 + post-rmw 11 = 18) is added to the exit code, so a wrong atomic encoding or a lost store changes it. the atomics run in _start, matching how the fixture already emits its inline-asm exit. verify.sh asserts the new exit code 71 and that lr.d / sc.d / amoadd.d disassemble as the real instructions (--mattr=+a enables the A-extension decode so the words are not <unknown>). Part of #1668.
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Adds the RV64A (atomic extension) subset to the riscv64 inline-asm assembler so std's riscv64 atomic arms (mach-std#308) can be expressed. Before this,
asm riscv64 { amoadd.d ...; lr.d ...; sc.d ... }failed withencode: unsupported riscv64 inline-asm mnemonic.What
lr.w/lr.d,sc.w/sc.damoswap/amoadd/amoand/amoor/amoxor/amomax/amomin/amomaxu/amominu, each.wand.d.aq/.rl/.aqrlon all of the abovepause(a fence hint) forspin_hintEncoding
The AMO major opcode (
0x2F) is R-type with the 5-bit funct5 in bits [31:27] and the aq/rl bits in [26:25], so the assembled funct7 is(funct5 << 2) | (aq << 1) | rl. Atomics use the base-only(rs1)address form (no displacement, unlike a regular load/store).lris the two-operandrd, (rs1)form (rs2 forced to x0);scand theamo*RMWs arerd, rs2, (rs1). The width (.w/.d) and ordering suffixes are parsed inline, so a future rv32 reuses the.wforms.Verification
inline_asm_atomicscovers every mnemonic and every ordering variant, byte-exact againstllvm-mc -triple=riscv64 -mattr=+a --show-encoding, plus the no-displacement and unsupported-amo-prefix rejections.test/riscv64with anlr/sccompare-and-swap loop and anamoadd.dRMW, asserting the result under qemu.mach test .passes; self-host fixpoint holds; x86_64/aarch64 unaffected.Closes #1668.
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