feat(sync/atomic): riscv64 arms#309
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Add riscv64 implementations for all 8 atomic ops, mirroring the x86_64/aarch64 arms: - load: full FENCEs bracket a plain aligned ld (seq-cst load) - store: amoswap.d.aqrl discarding the old value (seq-cst store) - cas: lr.d.aqrl/sc.d.aqrl retry loop - fetch_add: amoadd.d.aqrl - fetch_sub: neg then amoadd.d.aqrl (no amosub) - exchange: amoswap.d.aqrl - fence: fence - spin_hint: pause Each op uses the RISC-V A extension with .aqrl ordering for sequential consistency. Additive and comptime-gated, so x86_64/aarch64 are unaffected. Closes #308
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Closes #308
Adds riscv64 implementations for all 8 atomic ops in
src/sync/atomic.mach, mirroring the existing x86_64/aarch64 arms. Uses the RISC-V A extension with.aqrlordering for sequential consistency:fencebrackets a plain alignedldamoswap.d.aqrl zero, v, (ptr)(discards old)lr.d.aqrl/sc.d.aqrlretry loopamoadd.d.aqrlnegthenamoadd.d.aqrl(no amosub)amoswap.d.aqrlfencepauseAdditive and comptime-gated, so x86_64/aarch64 are unaffected.
Verification
mach test .-> 563/563 pass (all 12 atomic tests included).qemu-riscv64-> exit 0 (every assertion passed). Each instruction sequence was also unit-verified standalone under qemu.Requires a mach with RV64A inline-asm support (mach#1668, on mach
dev); CI seeds from the latest mach release, so this goes green once the riscv64 batch ships in v2.9.0.