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Highlights
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Pinned Loading
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YTU_Bilgisayar_Muhendisligi_Arsiv
YTU_Bilgisayar_Muhendisligi_Arsiv PublicYıldız Teknik Üniversitesi Bilgisayar Mühendisliği Bölüme Lisans ve Yüksek Lisansa Dair Genel Bilgiler, Ders Notları, Ders slaytları, Örnek Proje. Burada Staj, Erasmus, Yaz Okulu, KOOP gibi Kavraml…
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PCIe_Scrambler
PCIe_Scrambler PublicPCIe GEN1, GEN2 and GEN3 Scrambler, This Scrambler is able to scramble 1,2 and 4 bytes of data in 1 clock cycle in respect to the scrambling rules. Implemented in Verilog, Suitable for PIPE, Suppor…
Verilog 18
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PNR-CoreV1
PNR-CoreV1 PublicThis core was designed as a project in Processor Architecure lecture taught at UPC under Prof. Roger Espasa
Verilog 7
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gShare_Loop_Detector
gShare_Loop_Detector PublicThis branch predictor was designed as a project in Advanced Processor Architecure lecture taught at UPC under Prof. Antonio Gonzalez
C++ 1
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