drivers/network: add ixgbe driver#682
Conversation
This driver is for Intel X540/X550 NICs and works with IO-APIC and MSI/MSI-X interrupts. Signed-off-by: Terry Bai <tianyi.bai@unsw.edu.au>
Signed-off-by: Terry Bai <tianyi.bai@unsw.edu.au>
| config.virt_tx.active_queue.vaddr, | ||
| config.virt_tx.num_buffers); | ||
|
|
||
| // Disable Interrupts, see Section 4.6.3.1 |
There was a problem hiding this comment.
can we link the manual we are referncing somewhere for these sections to make sense?
| // Enable MSI. see PCI Express Technology 3.0 Chapter 17 for more details. | ||
| /* set_flags16(PCI_COMMAND_16, BIT(10)); */ | ||
| /* set_flags16(PCI_MSI_MESSAGE_CONTROL_16, BIT(0)); */ | ||
| /* clear_flags16(PCI_MSI_MESSAGE_CONTROL_16, BIT(4) | BIT(5) | BIT(6)); */ | ||
| /* set_reg(PCI_MSI_MESSAGE_ADDRESS_LOW, 0xFEEu << 20); */ | ||
| /* set_reg(PCI_MSI_MESSAGE_ADDRESS_HIGH, 0); */ | ||
| /* set_reg16(PCI_MSI_MESSAGE_DATA_16, 0x31); */ | ||
| /* clear_flags16(PCI_MSI_MASK, BIT(0)); */ | ||
|
|
||
| // Enable MSI-X, see PCI Express Technology 3.0 Chapter 17 for more details. | ||
| /* // Disable legacy interrupts. TODO: this should be done by PCI driver. */ | ||
| /* set_flags16(PCI_COMMAND_16, BIT(10)); */ | ||
| /* // Set vector message address to Local APIC of CPU0 */ | ||
| /* set_reg(DEVICE_MSIX_TABLE + 0x0, 0xFEEu << 20); */ | ||
| /* set_reg(DEVICE_MSIX_TABLE + 0x4, 0); */ | ||
| /* // Set vector data to Interrupt Vector */ | ||
| /* set_reg(DEVICE_MSIX_TABLE + 0x8, 0x32); */ | ||
| /* // Unmask vector 0 to enable interrupts through it */ | ||
| /* set_reg(DEVICE_MSIX_TABLE + 0xC, 0xFFFFFFFE); */ | ||
| /* // Enable MSI-X. TODO: this should be set by PCI driver. */ | ||
| /* set_flags(PCI_MSIX_CTRL, BIT(31)); */ |
There was a problem hiding this comment.
Either these are needed or not; there's no need for commented out code.
There was a problem hiding this comment.
As described in this PR, these are for manually switch which type of IRQs to use before a PCI driver is ready.
| while (!hw_tx_ring_empty()) { | ||
| /* Ensure that this buffer has been sent by the device */ | ||
| ixgbe_adv_tx_desc_wb_t hw_desc = device.tx_ring[device.tx_head].wb; | ||
| if ((hw_desc.status & IXGBE_ADVTXD_STAT_DD) == 0) |
There was a problem hiding this comment.
TODO: it is unclear to me whether we should use the head pointer to detect completion of Tx descriptor write back. According to section 7.2.3.5.2 of the X550 datasheet (rev. 2.7),
In legacy hardware, transmit requests are completed by writing the
DDbit to the transmit descriptor ring. This causes cache trash since both the driver and hardware are writing to the descriptor ring in host memory. Instead of writing theDDbits to signal that a transmit request is complete, hardware can write the contents of the descriptor queue head to host memory. The driver reads that memory location to determine which transmit requests are complete.
|
@terryzbai What's the current state on this PR? Is this just waiting on having a PCIe driver to be merged? |
That's one of the reasons. Another reason is that I haven't got time to look at the event logics, which seem different from other ethernet drivers that we have. Btw, it would be great for development if we have a machine with less booting time. |
4 participants
This driver is for Intel X540/X550 NICs and works with IO-APIC and MSI/MSI-X interrupts.
Before a proper PCI driver (#622) gets implemented, this experimental driver needs the access to PCI configuration space and set things up by itself. Interrupt types need to be manually switched by (un)commenting code snippets in
meta.pyandethernet.c.