IMX I2C driver#662
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add returh of data handler to imx i2c update i2c imx registers to align with data sheet memory map update i2c imx init step to use fast-mode divider add notes on i2c clock calculation update i2c imx driver to send start when await start update imx i2c address cycle handling add transmit successful check update boards.py to contain i2c region for imx add read handling in state_cmd_ret for i2c imx update i2c imx to set TXAK register when reading second to last byte
Signed-off-by: Lesley Rossouw <lesley.rossouw@unsw.edu.au>
…r why. Signed-off-by: Lesley Rossouw <lesley.rossouw@unsw.edu.au>
| I2C_BUS_NUM ?= 1 | ||
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| i2c_driver.elf: i2c/i2c_driver.o i2c/i2c_common.o | ||
| $(LD) $(LDFLAGS) $^ $(LIBS) -o $@ | ||
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| i2c/i2c_driver.o: CFLAGS+=-I${I2C_DRIVER_DIR} -DI2C_BUS_NUM=${I2C_BUS_NUM} |
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Yup. Replaced this with DTS parsing! Will remove
| ${CC} ${CFLAGS} -c -o $@ $< | ||
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| i2c/i2c_common.o: CFLAGS+=-I${I2C_DRIVER_DIR} | ||
| i2c/i2c_common.o: ${I2C_DRIVER_DIR}/../i2c_common.c |i2c $(SDDF_LIBC_INCLUDE) |
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this seems a bit weird with the relative paths
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The other i2c drivers are identical, so I will leave this as is. If we want to change it, worth an issue to do this to all of them.
| #define REG_CR_IEN (1 << 7) // I2C Enable | ||
| #define REG_CR_IIEN (1 << 6) // I2C Interrupt Enable | ||
| #define REG_CR_MSTA (1 << 5) // Master/Slave mode (1=Master, generates START when 0->1) | ||
| #define REG_CR_MTX (1 << 4) // Transmit/Receive (1=Transmit, 0=Receive) | ||
| #define REG_CR_TXAK (1 << 3) // Transmit Acknowledge (1=No ACK sent) | ||
| #define REG_CR_RSTA (1 << 2) // Repeat Start (1=Generate repeated START) | ||
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| // I2SR Status Register bits | ||
| #define REG_SR_ICF (1 << 7) // Transfer Complete (set at 9th clock falling edge) | ||
| #define REG_SR_IAAS (1 << 6) // Addressed As Slave | ||
| #define REG_SR_IBB (1 << 5) // Bus Busy (1=Busy, set by START, cleared by STOP) | ||
| #define REG_SR_IAL (1 << 4) // Arbitration Lost | ||
| #define REG_SR_SRW (1 << 2) // Slave Read/Write (1=Slave transmit) | ||
| #define REG_SR_IIF (1 << 1) // I2C Interrupt (set when byte transfer complete) | ||
| #define REG_SR_RXAK (1 << 0) // Received Acknowledge (1=No ACK received, 0=ACK received) |
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should probably use BIT(n) macro here
| // busy wait for ibb to clear ... | ||
| int timeout = 10000; | ||
| while ((regs->i2sr & REG_SR_IBB) && timeout-- > 0) {} |
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I suspect this was just done to be quick but we do generally not want to busy wait.
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Yeah correct. Theoretically this should never take longer than a few microseconds, and I personally think we ought to leave this as is until we have sdfgen able to support driver-to-driver dependencies so we can use a timer driver here nicely.
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| /** | ||
| * Send a start condition. This method should short circuit other writes to the CR register. |
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what does "short circuit" mean here?
is this related to the fact that you do |= and &= multiple times in the body here (to registers)
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"Short circuit" as in will overwrite outstanding operations. I will reword this to be more clear, the tldr is that you have to make sure the ops inside start land before doing anything else
Signed-off-by: Lesley Rossouw <lesley.rossouw@unsw.edu.au>
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This PR adds support for the I2C core of almost IMX8M boards. This was only tested on the IMX8MQ on the Maaxboard for now however, but theoretically this should work for all other IMX8MQ and IMX8Mmini boards.
On the Maaxboard, there is an odd quirk. Using any bus other than I2C1 (PMIC bus) causes the driver to silently hang. Consulting with @midnightveil and @Ivan-Velickovic leads me to believe that this is probably due to the other I2C buses being clock gated at boot.
This PR is a draft that we are rushing for a deliverable. We need to do the following things before merging: