drm: rockchip: dw_hdmi_qp: support inverted HDMI HPD - #559
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Included review availability: Your plan provides up to 2 included reviews per hour; 1 remains after this review. WalkthroughThe Core 3588E device tree sets Priority: ➖ Normal Estimated code review effort: 2 (Simple) | ~10 minutes Change: Bug fix Merge Risk: ⚪ Minimal · up to The Core3588E configuration applies HPD polarity inversion consistently in the interrupt and connector-status paths. No concrete merge-blocking issue remains. 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
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@rpardini The Actions failure looks like a runner issue rather than a compile error: the arm64 step succeeded, the armhf pass stopped at |
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Hello again. Thanks for this. When I did this board (which I don't have anymore), I used the "LEETOP carrier board" (as shown by https://www.cnx-software.com/2023/12/14/mixtile-core-3588e-development-kit-review-unboxing-first-boot/ ) -- from what I can remember HDMI worked fine. (It surely did on mainline kernel, which was done based on this). Maybe we should have a derivative DT (#include the original, override just the needed property) for a different carrier?
Yeah those CIs fail a lot. I guess some infra problem. I've Re-run. |
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@rpardini Thanks — and thanks for re-running the job. I think the carrier you used and the one I tested on are the same board. The review
That A206 is what's on my desk, so we're looking at the same SoM on the same carrier. Here's what I measure on it —
The bit tracks the cable inversely, so HPD is inverted on this carrier. With the On the derivative DT — I see the reasoning, but I don't think "#include the Happy to split it properly if we pick up a second carrier — a SoM I have the hardware here, so if there's anything you'd like checked, just say. |
Well, it's a bit out there but if you could also check the mainline DTs (back in armbian/build) it would be great. I don't have the Core3588E anymore, but a friend over in the US does. I have Blade3 and the Edge2 here to test. Both would benefit immensely from your knowledge -- both me and Joshua Riek have fiddled with them over the years, getting great mainline support would be awesome. For the Blade3, also the mainline u-boot needs love, I never got it stable due to the USB-C/TPCM FUSB302 powering -- it bootloops 3 out of every 5 times. I currently "shove" 12V down the USB-C port for stable operation. |
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@rpardini On the mainline front — we're already on it, in parallel with the We've been bringing these boards up on mainline in a Yocto layer (linux-yocto 6.18, U-Boot 2026.07), written from the schematics and validated on hardware per peripheral, with the full status documented in the layer README:
Build images for all three are tagged as releases, if you'd like to test them directly: Edge 2, Blade 3, Core 3588E. To be clear, this is just to show progress — it isn't going into this PR. The mainline changes are still being finalized on our end, and we'll submit them separately once they're ready. On the Blade3 power issue: we currently negotiate the PD contract in the kernel (the Blade3 DT already describes the two FUSB302 controllers, with |
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Ooops, @evtest-hash -- apparently conflict surfaced after merging the other changes, could you take a look? |
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I checked the conflict. It is only a textual conflict in the Core3588E The changes are additive, so both should be kept. The resolved node should be:
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Yep, thanks, still, this needs a rebase so we can merge. |
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On the Mixtile Core3588E used with a Jetson-compatible carrier board
(tested on a Seeed A206), HDMI hot plug detect is read with the wrong
polarity: the connector reports "connected" with nothing attached, and
"disconnected" once a display is plugged in.
The Core3588E passes SODIMM pin 96 straight through to the SoC with no
components in between, so the polarity is decided by the carrier, and on
Jetson-compatible carriers the HPD level shifter is inverting. This is
not a carrier defect. The NVIDIA Jetson TX2 NX Product Design Guide
(DG-10141-001_v1.1), figure 7-7 note 1, says:
"HPD level shifter can be non-inverting or inverting. HPD level
shifter on the Jetson TX2 NX Developer Kit is inverting."
The NVIDIA reference carrier implements HDMI HPD with a single NPN
common-emitter stage, which inverts; for DP/eDP, where the same guide
requires a non-inverting shifter, it uses two stages. This board shows
both sides of that split: &edp1 uses hpd-gpios with GPIO_ACTIVE_HIGH on
SODIMM pin 90, the non-inverting DP path, and needs no correction.
Add an optional "hpd-inverted" boolean. When present, the HPD level bit
is flipped straight after it is read from GRF_SOC_STATUS1, leaving all
downstream logic untouched. Both RK3588 HPD consumers need it: the
threaded HPD interrupt does not call read_hpd(), it evaluates the level
itself to set hpd_stat and to pick a direction-dependent debounce
(150 ms on connect, 20 ms on disconnect).
Measured on a Core3588E + A206. GRF_SOC_STATUS1 bit 16 tracks the cable
inversely, and the connector state is correct in both directions:
unplugged bit 16 = 1 disconnected 0 modes
plugged in bit 16 = 0 connected 47 modes, 3840x2160
Unplugging brings the VOP down on its own ("vop disable intf:800",
"Crtc atomic disable vp0") about two minutes before anything read sysfs,
so the interrupt path is exercised as well as the detect path.
Note this alone does not make HDMI work on the Core3588E: the board also
needs its HPD pin mux corrected from hdmim0_tx0_hpd (GPIO1_A5, the
rk3588s.dtsi default) to hdmim1_tx0_hpd (GPIO3_D4, where pin 96 lands),
which is handled separately.
Boards that do not set the property XOR the register value with 0, so
their behaviour is bit-identical to before. rk3588_hdmi_thread() and
dw_hdmi_rk3588_read_hpd() are RK3588-only; RK3538, RK3572 and RK3576 use
their own callbacks and are untouched.
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Depends on #556 for the Core3588E HDMI HPD pinmux correction (
hdmim0_tx0_hpd→hdmim1_tx0_hpd).Problem
On the Mixtile Core3588E used with a Jetson-compatible carrier (tested with a Seeed A206), HDMI HPD is electrically inverted. The Rockchip driver therefore reports
connectedwhen no display is attached anddisconnectedwhen a display is plugged in.Hardware
The Core3588E routes SODIMM pin 96 (
DP1_HPD) directly to the RK3588 HDMI HPD input. The carrier provides the HPD level shifter.The NVIDIA Jetson TX2 NX Product Design Guide (DG-10141-001_v1.1) explicitly allows either inverting or non-inverting HPD level shifters and states that the Jetson TX2 NX Developer Kit uses an inverting HPD level shifter.
Fix
Add an optional
hpd-invertedboolean to the RK3588 HDMI QP driver.When enabled, the HPD level read from
GRF_SOC_STATUS1is inverted before it is evaluated. Both RK3588 HPD handling paths apply the same polarity correction.When
hpd-invertedis absent, existing behaviour is unchanged.Validation
Tested on Mixtile Core3588E + Seeed A206 with a 4K display:
disconnectedconnected, EDID read successfullydisconnectedReal HDMI hotplug operation was verified.
Dependency
The Core3588E also requires the HPD pinmux correction from
hdmim0_tx0_hpdtohdmim1_tx0_hpd. That change is handled separately in #556.The two changes are independent:
Both are required for working HDMI on this board.
Both changes touch the same
&hdmi0node, so whichever merges second may show a small textual conflict there. The resolution is additive: keep the pinctrl configuration from #556 andhpd-invertedfrom this PR.Regression
hpd-invertedis only enabled for the Core3588E. When the property is absent, existing RK3588 and other supported SoC paths retain their current behaviour.