🖥️ MIPS Processor Implementations (VHDL)

📌 Overview

This repository contains multiple implementations of the MIPS (Microprocessor without Interlocked Pipelined Stages) architecture using VHDL.
The project is designed for educational and academic purposes, helping students understand CPU architecture and datapath/control design.

It includes Single-Cycle, Multi-Cycle, and 5-Stage Pipelined MIPS processors.

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📂 Repository Structure

32-bit-MIPS-processor/
│
├── Single-Cycle/ # Single-cycle MIPS processor
├── Multi-Cycle/ # Multi-cycle MIPS processor
├── Pipeline/ # 5-stage pipelined MIPS processor
└── README.md # Project overview

🧠 Implemented Architectures

🔹 Single-Cycle Processor

• Each instruction completes in one clock cycle
• Simple and clear datapath
• Ideal for learning CPU fundamentals
• Best for understanding datapath and control logic

📁 Folder: Single-Cycle/

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🔹 Multi-Cycle Processor

• Instructions are executed over multiple clock cycles
• Reuses hardware components across cycles
• More efficient than single-cycle in terms of clock period
• Demonstrates FSM-based control design

📁 Folder: Multi-Cycle/

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🔹 Pipelined Processor

• Classic 5-stage MIPS pipeline:
  • Instruction Fetch (IF)
  • Instruction Decode (ID)
  • Execute (EX)
  • Memory Access (MEM)
  • Write Back (WB)
• Includes:
  • Forwarding unit
  • Hazard detection
  • Stall insertion
• Higher instruction throughput compared to single-cycle

📁 Folder: Pipeline/

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🧩 Supported Instruction Types

• R-Type Instructions
• I-Type Instructions
• J-Type Instructions

(Details for each instruction set can be found inside the README of each folder.)

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🎯 Project Goals

• Understand MIPS architecture fundamentals
• Compare single-cycle, multi-cycle, and pipelined designs
• Learn datapath and control unit design using VHDL
• Practice hazard detection and resolution techniques
• Build a strong foundation in CPU microarchitecture

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🛠️ Technology Used

• Hardware Description Language: VHDL
• Design Style: Structural & Modular
• Target Use: Academic projects, learning computer architecture

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👥 Team Members

Abdulrahman Hussieni Single Cycle

Ahmed Hamed Single Cycle

Anas Mohamed Single Cycle

Mohamad Ahmad Hassan Single Cycle

Ahmed Ali Single Cycle

Amr Akmal PipeLine

Abdelrahman Ahmed PipeLine

Ahmed Mohamed PipeLine

Assem Melege PipeLine

Mohamed Eldeeb PipeLine