DQCE

The DQCE (Dynamic Quadrant Clock Enable) primitive in Gowin FPGA devices dynamically controls the internal logic's enablement, allowing GCLK0~GCLK5 to be turned on or off. When a GCLK is disabled, the internal logic driven by it will not toggle, reducing power consumption. Normal operation of the DQCE requires at least one falling edge change in the CLKIN signal, and it can be controlled via the CE (Clock Enable) input signal, which is active-high.

This device is supported in Apicula.

Ports

Port	Size	Direction
CE	1	input
CLKIN	1	input
CLKOUT	1	output

Verilog Instantiation

DQCE dqce_inst (
    .CE(CE),
    .CLKIN(CLKIN),
    .CLKOUT(CLKOUT)
);