30-second version: TLDR.md
Status: v3. Experiments 001 and 002 are archived; that board and that memory left service, so the original captures are what survives of those runs. Experiment 003 is verified as of 2026-09-17 with dated benchmark, stability and timing-readout evidence. Experiment 004 closed on 2026-09-21: the ceiling of a 96GB dual-rank configuration on this platform is 6200 C26.
I am a high-school student and a DDR5 overclocking hobbyist. This repository is my lab notebook: the settings I ran, what the machine did, and where the limits turned out to be. I write each run down because a memory number means nothing without its conditions attached, and because the written record is what catches the cases where two runs disagree with each other.
Four experiments so far (001 and 002 share the archived platform):
- Archived (96GB Hynix M-die, ASUS TUF B850M-Plus). EXPO 6000 CL28 to tuned 6200 CL26 synchronous (
26-36-36-36-38aggressive /26-37-37-37-38rock solid, 1.54 V, FCLK 2067 daily). AIDA64 latency: ~90 ns at EXPO (recalled) to 67.6 ns best. - Verified (32GB Hynix A-die, ROG Crosshair Apex X870E). EXPO 6400 C30 to 8000 C36 asynchronous at 1.575 V, BCLK 102. AIDA64 latency 68.2–68.6 ns, four clean 30-minute stability runs.
- Closed (96GB dual-rank, Apex X870E). 6200 C26 synchronous at 1.515 V is the ceiling of this configuration. 6400 fails on both the 9800X3D and the 9950X3D (three of five attempts inside the first eight seconds of the first test), and 8000 async does not POST at all. The 96GB kit stays for capacity; the 32GB single-rank kit remains the high-frequency vehicle.
| Term | Meaning |
|---|---|
| EXPO | AMD's one-click memory profile in the BIOS (the same idea as Intel XMP) |
| MCLK / UCLK / FCLK | DRAM clock, memory-controller clock, Infinity Fabric clock. Synchronous means UCLK = MCLK |
| Rank | a group of DRAM chips that answers together; a 48GB module is usually dual rank |
| IMC | integrated memory controller, on the CPU die |
| POST | power-on self-test, the board's boot check before the OS loads |
| Component | Detail |
|---|---|
| CPU | AMD Ryzen 7 9800X3D |
| Motherboard | ASUS ROG Crosshair Apex X870E, BIOS 2402 (AGESA 1.3.0.1b Patch A) |
| Memory | 32GB G.Skill Trident Z5 Royal Neo (Hynix A-die, 16GB × 2, single rank, factory EXPO 6400 C30) |
| Cooling | CPU water (AIO); onboard memory fan, DIMMs peak at 58 °C / 60 °C under a 30-minute stability run |
| OS | Windows 11 |
iGPU note: with the Ryzen iGPU enabled the OS reserves 3 GiB (visible total 29,364 MB versus 32,436 MB with it disabled). It only affects latency results when the display is driven by it.
| Component | Detail |
|---|---|
| Memory | OC Lab OCL602696D-VB, 96GB dual rank (48GB × 2); the vendor markets specially binned ICs |
| Ceiling established | 6200 MT/s synchronous, C26 (26-36-36-36-72), 1.515 V, FCLK 2067. 6400 synchronous fails on both CPUs tested; 8000 async does not POST |
| VSOC | read back by ZenTimings as 1.2000 V on the passing 6200 frame and 1.2500 V on the 6400 attempts. ZenTimings reports the SMU rail rather than the BIOS setting, so I quote it per frame |
| Component | Detail |
|---|---|
| CPU | AMD Ryzen 7 9800X3D (the same CPU) |
| Motherboard | ASUS TUF B850M-Plus, BIOS 1001 |
| Memory | 96GB G.Skill Trident Z5 Royal Neo (Hynix M-die, 48GB × 2, factory EXPO 6000 C28) |
| Cooling | CPU water (AIO); memory passively cooled. Kept ≤ 1.55 V and under 60 °C in stress tests |
- 001 — Baseline: EXPO 6000 CL28 (96GB, B850M) (archived)
- 002 — 6200 CL26 (96GB, B850M) (archived)
- 003 — 8000 C36 (32GB, Apex X870E) (verified 2026-09-17)
- 004 — OC Lab 96GB dual-rank on the Apex (closed: 6200 C26 daily, 6400/8000 out of reach)
- AIDA64: latency / bandwidth benchmarks
- ZenTimings: timing and voltage read-out
- TestMem5 / RunMemtestPro: stability testing
- HWiNFO: temperature and voltage logging
| Experiment | Configuration | Frequency | Primaries (tCL-tRCDWR-tRCDRD-tRP-tRAS) | Voltage | Read / Write / Copy | Latency |
|---|---|---|---|---|---|---|
| 001 | EXPO | 6000 MT/s | 28-36-36-96 (EXPO) | 1.35 V | not recorded | ~90 ns (recalled) |
| 002 | Tuned, sync | 6200 MT/s | 26-36-36-36-38 (aggressive) / 26-37-37-37-38 (rock solid) | 1.54 V | 68.2 / 91.4 / 67.0 GB/s (best sample) | 67.6 ns best, 67.6–70.8 ns observed |
| 003 | Tuned, async | 8000 MT/s | 36-48-48-48-96 | 1.575 V | 63.9 / 45.3 / 58.7 GB/s | 68.2–68.6 ns |
| 004 | Tuned, sync | 6200 MT/s | 26-36-36-36-72 | 1.515 V | not measured | not measured |
Two caveats on that table, both about the 002 row. The 67.6 ns best sample came from the aggressive primary set; the rock-solid set has no AIDA64 capture of its own, only the timing read-out. And the ~25% latency reduction over the baseline (90 → 67.6 ns) rests on a baseline figure I wrote down at the time and cannot show: see Experiment 001. The 004 row carries no benchmark for a different reason: no 6400 configuration was ever stable enough to measure, and the 6200 daily profile was recorded through TestMem5 and ZenTimings only.
AM5 gives two ways to run a DDR5 kit.
- Synchronous: UCLK = MCLK, tighter possible primaries, much easier to stabilise. At 6400 MT/s that means UCLK = MCLK = 3200; FCLK is a separate rail (2133 is the 1:3 point at that frequency). This CPU's IMC did not hold 6400 on either kit I ran. Raising FCLK above the 1:3 point was separately unstable here: 2167 or higher never held, even at 1.53 V with VSOC set to 1.25 V.
- Asynchronous: UCLK = MCLK / 2 at high frequency, with looser primaries and tertiary timings that are barely moved. It sidesteps the FCLK wall, which is how the Apex board runs 8000 C36.
The two routes converge on latency: 6200 C26 synchronous measured 67.6 ns, and 8000 C36 asynchronous measures 68.2–68.6 ns, so latency does not fall with frequency here. Nor did the async build add bandwidth on the recorded samples: it reads and copies less (63.9 and 58.7 GB/s against 68.2 and 67.0 GB/s for the archived synchronous build), and its write figures are FCLK-bound and moved together with the rank count, the frequency and the AIDA64 version, so they are not directly comparable.
The 6400 wall looks like it sits on the controller side. Both kits were tested at 6400 and both failed: the 32GB A-die kit at its own factory EXPO (6400 C30, a speed the factory validates) and the 96GB M-die kit tuned to 6400. That same 32GB kit later ran 8000 C36 on the Apex board. 6200 C26 was therefore the practical optimum on that platform: stability, temperature and usability over the last few hundred MT/s.
FCLK is not monotonic. Community sweeps at fixed memory frequency show a first sweet spot at the 1:3 ratio, a plateau or a slight regression one or two steps above it, and latency improving again only well above that. At 6200 MT/s here, FCLK 2067 and 2133 measured the same latency, and a real gain needed 2167 or higher, which this IMC never held. The archived profile therefore ran 2067 daily and 2133 as the validated maximum. Write bandwidth moves with FCLK as well: 6200 with FCLK 2133 wrote 84–94 GB/s, while 8000 with FCLK 2000 writes 45 GB/s. Rank count and the AIDA64 version changed at the same time as the FCLK did, so I read that as an association rather than a clean single cause.
Experiment 003 (verified 2026-09-17, TestMem5 v0.13.1, profile Universal 2 @ LMhz, 6 threads, 30-minute budget):
| Started | Duration | Cycles | Errors | Outcome |
|---|---|---|---|---|
| 2026-08-02 22:32 | 35:00 | — | 0 | Testing completed |
| 2026-08-03 14:28 | 35:44 | — | 0 | Testing completed |
| 2026-09-16 22:40 | 33:19 | — | 0 | Testing completed |
| 2026-09-16 23:19 | 33:42 | 6 | 0 | Testing completed |
Peak DIMM temperatures during the retained run: 58.0 °C and 60.0 °C. Tuning-phase runs that reported errors stay in the same log rather than being discarded, but the log does not record which configuration each run used, so published runs are paired with dated ZenTimings/AIDA64 captures from here on.
Experiment 002 (archived, 96GB M-die on B850M: passively cooled, voltage capped at 1.55 V, case fans at full speed):
| Tool | Profile | Duration / Coverage | Max DIMM temp | Errors |
|---|---|---|---|---|
| TestMem5 v0.13.1 | default | 30 min | ≤ 61 °C | 0 |
| TestMem5 v0.12 | default | 3 cycles | ≤ 61 °C | 0 |
| RunMemtestPro | — | run completed | ≤ 61 °C | 0 |
Those three rows are my own observations rather than logged evidence: the v0.13.1 log for that kit has no completed 30-minute entry, the v0.12 log records sizes and outcomes but no dates, and RunMemtestPro left no log at all.
Above roughly 61 °C that kit starts erroring, which is what the voltage cap and the airflow were there to prevent. Daily workloads never saturate memory the way a stress test does, since module power tracks utilisation, so daily use stayed well inside the envelope.
Impressions from daily use on Experiment 002 (EXPO → 6200 CL26, 96GB). No controlled A/B, one machine, nothing logged, so read these as rough impressions rather than measurements; the latency figures above are the rigorous metrics.
| Workload | Improvement |
|---|---|
| Online games | ~+20% |
| GPU-bound 3A titles | ~+5% |
| Video editing | ~+10% |
| Small LLM loading | ~+25% |
Results depend on CPU IMC quality, motherboard, memory ICs, capacity, cooling and voltage, so every number here is specific to this hardware and none of it is a general claim. High-capacity dual-rank kits are harder to tune than single-rank 32GB kits. Experiments 001 and 002 cannot be re-run as originally configured: that memory and that board are gone, and what survives is the original captures plus two TestMem5 logs. The ~90 ns EXPO baseline in particular has no surviving capture.
- Experiment 004 (closed): the 96GB dual-rank ceiling on this platform is 6200 C26 at 1.515 V. 6400 synchronous fails within seconds on two CPU samples and 8000 async will not POST, so the limit looks like the four-rank configuration rather than any one CPU. Revisit only with new levers: CLDO VDDP sweep (never moved off 0.9472 V), ODT/impedance sweep, tRFC scaling at 6400, and a 6300 MT/s point to bracket the ceiling.
- Test whether the archived below-floor tRAS (38 against a tRCD+tRP floor of 74) actually cost latency: one BIOS change, one benchmark.
- Measure the iGPU on/off latency delta on this platform (expected nil with the display on the discrete GPU).
- Push past 8000 C36: C34 and 8400 C36 are reachable but fail stability, so further IMC and kit exploration.
- Keep the stability record self-describing: a dated log entry paired with a dated timing/voltage read-out.
- Explain the one-off freeze observed after a clean 30-minute run (see Experiment 003, open questions).
A DDR5 overclocking lab notebook on AM5: four experiments; 003 verified (2026-09-17), 004 closed at its best stable setting (2026-09-21).
- experiments/003-8000-c36.md: what 8000 MT/s asynchronous bought a 32GB kit (latency 68.2-68.6 ns vs 67.6 for the archived build; read bandwidth 63.9 vs 68.2 GB/s, no gain).
- experiments/004-96gb-apex.md: how far a 96GB dual-rank kit goes (6200 C26 at 1.515 V; 6400 fails on both CPUs, fastest error at 0:00:04; 8000 async never boots).
- data/benchmark.csv: all benchmark numbers (002 final state: 6200 MT/s, 26-36-36-38, 1.54 V, 67.6 ns).
Check it yourself: assets/raw/tm5-Log-202601-0918-0011.txt lines 176-179: 003's retained 8000 C36 run ends 0:33:42 Testing completed, no error line.
Limits: stability means 0-error TestMem5 runs of 33-48 minutes, not multi-hour soak tests.
Summary: TLDR.md.
MIT — see LICENSE.