Papers, Posters, Presentations, Documentation...
See README_jade for information about our generation-1 (Genesis2-based) CGRA chip Jade.
Garnet is the SoC containing our second-generation (magma-based) CGRA, which is targeted to reside within an SoC.
- Garnet - AHA SoC containing second-generation CGRA
- Lassen - PE used in Garnet
- Gemstone - Chip generator infrastructure based on Magma
- Peak - Specification language for processing elements (CPUs)
- Canal - Specification language for intertile routing
- Magma - A hardware design language embedded in python
- Fault - A Python package for testing hardware (part of the magma ecosystem)
Combined flow
- End-to-end compile, build, run (StanfordAHA/GarnetFlow)
Software flow
- Target applications for the CGRA (StanfordAHA/Applications)
- Halide apps and test cases (StanfordAHA/CGRAFlowDoc)
- Halide front end (Halide->CoreIR) (StanfordAHA)
CoreIR mapper (CoreIR->CoreIR) (StanfordAHA)- CoreIR mapper (CoreIR->CoreIR) (rdaly)
- CoreIR primitives (StanfordAHA)
- PNR (CoreIR->bitstream (b)) (Kuree) [1]
- Thunder placement engine (Kuree)
- Cyclone routing engine (Kuree)
Harware flow
- Gemstone CGRA generator infrastructure (StanfordAHA)
- Garnet next-gen CGRA generator (StanfordAHA)
- Lassen CGRA processing element (StanfordAHA)
- Peak DSL for CPU specification (phanrahan)
- Canal DSL for intertile routing (StanfordAHA)
Tools and testing
- Magma generator framework (phanrahan)
- Magmathon for learning Magma (phanrahan)
- Fault Python pkg for testing hw leonardt
- Fault tutorial leonardt
Footnotes
[1] PNR repo will probably move to StanfordAHA at some point