RISC-V RV32I Single-Cycle Processor

A 32-bit RISC-V processor (RV32I ISA) implemented from scratch in Verilog. Single-cycle architecture, simulation-based with Icarus Verilog.

Architecture

PC → Instr Mem → Control + Decode → Register File → ALU → Data Mem → Writeback

Modules: ALU, register file, program counter, immediate generator, control unit, instruction/data memories, top-level CPU.

Usage

# Run full simulation (sum of 1 to 10)
make

# Run individual module tests
make test_alu
make test_regfile
make test_pc
make test_imm_gen

# View waveforms
make wave

make clean

Tools

• Icarus Verilog — simulation
• Surfer — waveform viewer