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Five stages Pipeline Processor

📝 Table of Contents

About

The processor in this project has a RISC-like instruction set architecture. There are eight 2-bytes general purpose registers[ R0 to R7]. These registers are separate from the program counter and the stack pointer registers. The program counter (PC) spans the instructions memory address space that has a total size of 2 Megabytes. Each memory address has a 16-bit width (i.e., is word addressable). The instructions memory starts with the interrupts area (the very first address space from [0 down to 2^5-1]), followed by the instructions area (starting from [2^5 and down to 2^20]) as shown in Figure.1. By default, the PC is initialized with a value of (2^5) where the program code starts.

Project Design

design

Design.pdf

Implemented Instructions

☝️ One Operand

NOP
SETC
CLRC
NOT Rdst
INC Rdst
DEC Rdst
OUT Rdst
IN Rdst

✌️ Two Operands

MOV Rsrc, Rdst
ADD Rsrc, Rdst
SUB Rsrc, Rdst
AND Rsrc, Rdst
OR Rsrc, Rdst
SHL Rsrc, Imm
SHR Rsrc, Imm

💾 Memory

PUSH  Rdst
POP  Rdst
LDM  Rdst, Imm
LDD Rsrc, Rdst
STD Rsrc, Rdst

🦘 Jumps

JZ  Rdst
JN  Rdst
JC Rdst
JMP  Rdst
CALL Rdst
RET
RTI

Input Signals

Reset
Interrupt

Contributors

Asmaa Adel
Asmaa Adel
Asmaa Adel
Samaa Hazem
norhan reda
norhan reda
HodaGamal
HodaGamal

About

A simple 5-stage pipelined processor following Harvard's architecture. The processor has RISC-like ISA.

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  • Verilog 62.0%
  • Stata 20.3%
  • Python 13.1%
  • Assembly 4.3%
  • Batchfile 0.3%