Heterogeneous Multicore by yim13 · Pull Request #135 · Purdue-SoCET/RISCVBusiness

yim13 · 2025-12-11T19:38:29Z

This adds heterogeneous multicore configuration feature with extensions and caches, riscv-tests pm environment support from tb_core.cc and run_riscv_tests.py, clock gating, and C multicore tests.

For riscv-tests to be run correctly, pull requests in riscv-test/ and riscv-test/env rvb branch needs to be applied.

…support upto 8 cores

Small edits to adjust to updated pkg file

* riscbusiness: split buses into front and back sides quartus randomly assigned to all of the split bus signals in each instantiation of the caches causing a large number of build errors. This splits the bus into a front side that connects back_side<->RISCVBusiness and a back side that connects RISCVBusiness<->bus controller. * [misc] fixing failing riscv-tests * component_defines: rename address_translation_enabled to address_translation Helps deal with quartus not properly supporting generate compile time instantiation * misc: various fixes for quartus * [cleanup] renaming supervisor_enabled to supervisor, fixing build issues --------- Co-authored-by: William Cunningham <wrcunnin@purdue.edu>

* [misc] initial commits to fixing aft-dev FPGA build * [misc] fixing riscv-test failures - includes updates to tb_core.cc, changed virtual to debug. - includes updates to riscv-test isa and env patches - multicore (2-harts) now passes integer and multiplication virtual and physical tests, and atomic physical - (virtual atomic tests don't work due to amo_emu.c) * riscv-tests-env.patch: ignore pointer cast warning --------- Co-authored-by: Devin Singh <drsingh2518@icloud.com>

wrcunnin

How exhaustive has your testing been? Just want to make sure that if you max out one core (like 2KB caches, 2 way associative, 4-word blocks, 64 entry BTB) and weaken another (256B caches, 1 way, 2-word block, 16 entry BTB, etc.) that in the package and waveforms this is what actually gets generated.

Can you also link your presentations here?

wrcunnin · 2025-12-19T16:26:49Z

+  - `xlen`
+  - Bus type and endianness
+  - Cache block sizes
+  - Supervisor and address translation settings


I think we should loop TLB size into the per-core configuration. It would make more sense so we can put it with the other caching structures. I can help with this.

wrcunnin · 2025-12-19T16:33:26Z

@cole-nelson should we merge this with the normal core config script?

Definitely needs to be merged into old core config

wrcunnin · 2025-12-19T16:34:42Z

see my comment on hetero_config_core.py. this may get reverted depending on that.

wrcunnin · 2025-12-19T16:37:21Z

Any diagrams to include with this? Would be good to have visuals for an example heterogeneous core layout with clock gating.

wrcunnin · 2025-12-19T16:37:41Z

- [ ] 2 stage pipeline RV32EAC little core
-
 ## Current architecture plan for the Dual-core processor with MESI Coherence
 ![Plan](../fig/mc_arch_idea.png)


@cole-nelson we should get this updated to use the diagram you used for AFTx08 presentation.

wrcunnin · 2025-12-19T17:25:29Z

go ahead and revert this as well

wrcunnin · 2025-12-19T17:27:59Z


+    if(num_harts > 1) {
+        // write to memory about required extension info
+        memory.write(tohost_address + 64, 1 << (extension - 'A'), 0xFF);


why not use FROMHOST_OFFSET here?

wrcunnin · 2025-12-19T17:46:14Z

        }
+
+        if(use_tohost_multi) {
+            if(tohost_address <= addr <= tohost_address + FROMHOST_OFFSET && (addr - tohost_address) % tohost_stride == 0) {


@cole-nelson i'm no c++ whiz, is this functionally sound?

Nope. Needs to be tohost_address <= addr && addr <= (tohost_address + FROMHOST_OFFSET) && (addr - tohost_address) % tohost_stride == 0

wrcunnin · 2025-12-19T17:48:47Z

    std::cout << "\t--debug  : Allows debug strings to print from cores. Changes tohost-address functionality" << std::endl;
    std::cout << "\t--notrace: Indicate to not generate a waveform file. Speeds up simulation incredibly." << std::endl;
+    std::cout << "\t--num-harts : Number of cores for multicore test. Defaults to 1." << std::endl;
+    std::cout << "\t--extension : RISC-V extension required for the core to run the test. Running pm env tests require this flag to run correctly." << std::endl;


add something like <sim-time> for --max-sim-time. we need to clarify that we have a field that is to come after it.

wrcunnin · 2025-12-19T17:54:52Z

delete this, we generally give these files the extension .dump and our .gitignore picks it up.

devins2518

To be done before merging:

Rebase onto master
Revert to example.yml (actually I think core_configuration.yml is a better name)
Update riscv-tests SHA
Update AFT and ensure that this doesn't break anything there

devins2518 · 2025-12-26T04:19:22Z

Definitely needs to be merged into old core config

devins2518 · 2025-12-26T04:35:57Z

Instead of passing the HART_ID everywhere, could we instead create a struct to pass relevant args through the hierarchy?

Something like

typedef struct { bool RV32M; ... } isa_config_t; typedef struct { ... } cache_config_t; typedef struct { int HART_ID; isa_config_t isa_config; cache_config_t cache_config; ... } core_config_t; const core_config_t HART0_CONFIG = '{ ... }; const core_config_t HART1_CONFIG = '{ ... }; const core_config_t CONFIGS[NUM_HARTS] = {HART0_CONFIG, HART1_CONFIG}; ... RISCVBusiness #(.CONFIG(CONFIGS[HART_ID])) hart (...);

Now the caches will take in a cache_config_t to handle configuration. I think it'll create a stronger link between the config and instantiations and hopefully avoid any potential foot guns from not using a core config parameter.

devins2518 · 2025-12-26T04:36:38Z

Yeah should replace component_selection_defines.vh

devins2518 · 2025-12-26T04:38:42Z

What does extension_idx_t do?

devins2518 · 2025-12-26T04:43:03Z

+                .product(product),
+                .finished(mul_finished)
+            );
+        end


I think it's probably cleaner if we use enums to define the possibilities instead of strings. Then it becomes a switch on known values. Could be future work though

devins2518 · 2026-01-15T18:38:45Z

        }
+
+        if(use_tohost_multi) {
+            if(tohost_address <= addr <= tohost_address + FROMHOST_OFFSET && (addr - tohost_address) % tohost_stride == 0) {


Nope. Needs to be tohost_address <= addr && addr <= (tohost_address + FROMHOST_OFFSET) && (addr - tohost_address) % tohost_stride == 0

devins2518 · 2026-01-15T18:39:07Z

+        // if (addr == FROMHOST_ADDR) {
+        //     return 1;
+        // }


devins2518 · 2026-01-15T18:40:11Z

    std::cout << "\t--debug  : Allows debug strings to print from cores. Changes tohost-address functionality" << std::endl;
    std::cout << "\t--notrace: Indicate to not generate a waveform file. Speeds up simulation incredibly." << std::endl;
+    std::cout << "\t--num-harts : Number of cores for multicore test. Defaults to 1." << std::endl;
+    std::cout << "\t--extension : RISC-V extension required for the core to run the test. Running pm env tests require this flag to run correctly." << std::endl;


What is the purpose of --extension?

devins2518 · 2026-01-15T18:44:04Z

+        .core_clk_en(core_clk_en)
+    );
+
+    assign pipeline_clk = CLK & core_clk_en;


Little sketch to me

devins2518 · 2026-01-15T18:55:49Z

Do we even support standalone RISCVBusiness for FPGA?

devins2518 · 2026-01-15T19:35:32Z

Tests failing for me with updated riscv-tests (hetero-multicore branch)

Seongjoong Yim and others added 30 commits October 28, 2025 14:08

multicore_tests: Updated matrix multiplication and mergesort test to …

bec5933

…support upto 8 cores

updated example file for per core vs non per core configs

6327633

changes to this test

23fcd39

Created sample core config package file for config script reference

c867aa8

fixed core_configuration_pkg syntax

5149ec9

Added parameter to take HART_ID for core configuration

e62c3e1

core_cofig: fixed packed struct order

d376a45

Updated ifdefs with generate blocks

a3fa509

Create hetero_config_core.py

c3ab7ed

Updated to support config core

053f99f

fixed string

6e1d857

Updates for core configs

4512ec0

Update hetero_config_core.py

5b87fe3

Small edits to adjust to updated pkg file

fixing output paths

9fd2ca8

Update caches_wrapper.sv to work for hetero

7bf4ff4

Update dcache_type and icache_type

7816cd9

Update hetero_config_core.py to include riscmgmt extentions

2a08134

changes to caches and example f file

4342a19

Update hetero_config_core.py tlb and noncache

ca412f4

Delete waveform.fst.hier

c4b6662

Delete .venv directory

1e17fec

Include CPUS and DATA_WIDTH params

77b6d96

Adding per core params

29e34a5

Update config_core_hetero.py

deb59b3

Delete scripts/config_core_hetero.py

7472aad

Add cpu and data_width params

8236230

added SMODE_ENABLED

8b37893

fixed unnecessary HART_ID params

8ff8f53

aishuanand01 and others added 19 commits December 9, 2025 17:50

adding parameter fix

8c79b93

fix parameter instantiation

fcfce72

fix parameter instantiation

60e73e6

add core_clk_gating

a23eb48

fixing pin

a18682d

remove flag and shared values

5c9607e

lots of changes to make clock gating work

4fd57b6

clk gating working now

28abcdf

Delete verification/multicore-tests/c-tests/waveform.fst.hier

609a0e1

Delete verification/multicore-tests/c-tests/core_clk_gating_tb.asm

06b1357

Delete verification/multicore-tests/c-tests/core_clk_gating_tb.s

dfda2ac

Delete verification/multicore-tests/c-tests/compute_bound.dump1

2bd0d58

Delete verification/multicore-tests/c-tests/.venv directory

1759633

fpga setup

e6837e9

config script cleanup

e41f3e0

cleanup for pr

c76d647

Update core configuration Makefile

26ac47d

clean up

fa1e5da

fixed wrong indexing

cc42133

yim13 requested review from cole-nelson, devins2518 and wrcunnin December 11, 2025 19:38

Seongjoong Yim and others added 5 commits December 12, 2025 02:44

heterogeneous multicore wiki

e2c4346

doc update

5665fcd

small updates

14972a4

editing some stuff

75b518f

formating

0a6496e

wrcunnin requested changes Dec 19, 2025

View reviewed changes

devins2518 requested changes Jan 15, 2026

View reviewed changes

Conversation

yim13 commented Dec 11, 2025

Uh oh!

wrcunnin left a comment

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

devins2518 left a comment • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

devins2518 commented Jan 15, 2026

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

4 participants

devins2518 left a comment •

edited

Loading