[Raghavan-04]

Summary

Added SystemVerilog functional coverage module (timer_cov.sv) bound to apb_timer_wrapper in apb_timer_tb_top.sv.

Related issue or proposal

Related to #1

Design notes

• Non-Intrusive Integration: Bound timer_cov to apb_timer_wrapper inside apb_timer_tb_top.sv to keep verification logic separated from synthesizable RTL.
• Control & Prescaler Coverage (cg_ctrl): Tracks timer_en, oneshot_en, and pwm_en crossed with prescaler value bins (zero, one, max, mid_range).
• Register Configuration (cg_timer_cfg): Tracks reload vs. compare threshold conditions (compare < reload, compare == reload, compare > reload).
• Interrupts & Masking (cg_irq): Tracks overflow (irq_stat[0]) and compare match (irq_stat[1]) triggers, crossed with mask enables (irq_en).

Verification

Static linting executed cleanly via Verilator in Linux GitHub Codespaces:

verilator --language 1800-2017 --lint-only -f .rtl_filelist.f --top-module apb_timer_wrapper
# Output: Exit code 0 (0 warnings, 0 errors)

Checklist

• Scope was discussed before implementation when required.
• RTL is synthesizable and follows the repository style.
• Reset, errors, backpressure, and corner cases were considered.
• Tests fail without the fix where this is a bug fix.
• UVM/assertions/coverage were updated where applicable.
• Lint, compile, simulation, and relevant regressions pass.
• Documentation and register descriptions are current.
• Commits are focused, atomic, and free of unrelated changes.
• New code is original or correctly licensed and attributed.

[Raghavan-04]

Hi @briann-bui,

Thank you for the detailed feedback! I have updated the PR to address all review points:

1. Fixed Coverage Bind: Updated apb_timer_tb_top.sv to correctly bind timer_cov to the actual wrapper/interface signals (i_timer_pclk, i_timer_presetn, w_timer_*, u_apb_if.r_irq_*, and o_timer_pwm).
2. Reset Gating: Secured all covergroups (cg_ctrl, cg_timer_cfg, cg_irq) with iff (rst_n) to prevent reset and X value pollution.
3. PWM, Counter & W1C Coverage: Implemented full coverage for timer_val states (zero, mid, max), pwm_out level toggles, Write-1-to-Clear transitions (1'b1 => 1'b0) for both overflow and compare IRQ bits, and expanded interrupt mask cross-coverage.
4. Testbench Compilation: Added uvm/tb/timer_cov.sv to filelist.f to ensure complete compilation coverage.

All CI checks are passing successfully. Ready for re-review!