mb/google/*: Add CFR options for Intel ME HECI1 and PAVP

src/mainboard/google/brox/cfr.c

@@ -15,6 +15,8 @@ static struct sm_obj_form system = {
 		&legacy_8254_timer,
 		&me_state,
 		&me_state_counter,
+		&me_heci1,
+		&me_pavp,
 		&pciexp_aspm,
 		&pciexp_clk_pm,
 		&pciexp_l1ss,

src/mainboard/google/brya/cfr.c

@@ -42,6 +42,8 @@ static struct sm_obj_form system = {
 		&legacy_8254_timer,
 		&me_state,
 		&me_state_counter,
+		&me_heci1,
+		&me_pavp,
 		&pciexp_aspm,
 		&pciexp_clk_pm,
 		&pciexp_l1ss,

src/mainboard/google/dedede/cfr.c

@@ -38,6 +38,8 @@ static struct sm_obj_form system = {
 		&legacy_8254_timer,
 		&me_state,
 		&me_state_counter,
+		&me_heci1,
+		&me_pavp,
 		&pciexp_aspm,
 		&pciexp_clk_pm,
 		&pciexp_l1ss,

src/mainboard/google/drallion/cfr.c

@@ -21,6 +21,8 @@ static struct sm_obj_form system = {
 		&legacy_8254_timer,
 		&me_state,
 		&me_state_counter,
+		&me_heci1,
+		&me_pavp,
 		&pciexp_aspm,
 		&pciexp_clk_pm,
 		&pciexp_l1ss,

src/mainboard/google/eve/cfr.c

@@ -15,6 +15,8 @@ static struct sm_obj_form system = {
 		&legacy_8254_timer,
 		&me_state,
 		&me_state_counter,
+		&me_heci1,
+		&me_pavp,
 		&pciexp_aspm,
 		&pciexp_clk_pm,
 		&pciexp_l1ss,

src/mainboard/google/fizz/cfr.c

@@ -21,6 +21,8 @@ static struct sm_obj_form system = {
 		&legacy_8254_timer,
 		&me_state,
 		&me_state_counter,
+		&me_heci1,
+		&me_pavp,
 		&pciexp_aspm,
 		&pciexp_clk_pm,
 		&pciexp_l1ss,

src/mainboard/google/glados/cfr.c

@@ -15,6 +15,8 @@ static struct sm_obj_form system = {
 		&legacy_8254_timer,
 		&me_state,
 		&me_state_counter,
+		&me_heci1,
+		&me_pavp,
 		&pciexp_aspm,
 		&pciexp_clk_pm,
 		&pciexp_l1ss,

src/mainboard/google/hatch/cfr.c

@@ -35,6 +35,8 @@ static struct sm_obj_form system = {
 		&legacy_8254_timer,
 		&me_state,
 		&me_state_counter,
+		&me_heci1,
+		&me_pavp,
 		&pciexp_aspm,
 		&pciexp_clk_pm,
 		&pciexp_l1ss,

src/mainboard/google/octopus/cfr.c

@@ -18,6 +18,8 @@ static struct sm_obj_form system = {
 		&legacy_8254_timer,
 		&me_state,
 		&me_state_counter,
+		&me_heci1,
+		&me_pavp,
 		&pciexp_aspm,
 		&pciexp_clk_pm,
 		&pciexp_l1ss,

src/mainboard/google/poppy/cfr.c

@@ -36,6 +36,8 @@ static struct sm_obj_form system = {
 		&legacy_8254_timer,
 		&me_state,
 		&me_state_counter,
+		&me_heci1,
+		&me_pavp,
 		&pciexp_aspm,
 		&pciexp_clk_pm,
 		&pciexp_l1ss,

src/mainboard/google/puff/cfr.c

@@ -16,6 +16,8 @@ static struct sm_obj_form system = {
 		&legacy_8254_timer,
 		&me_state,
 		&me_state_counter,
+		&me_heci1,
+		&me_pavp,
 		&pciexp_aspm,
 		&pciexp_clk_pm,
 		&pciexp_l1ss,

src/mainboard/google/reef/cfr.c

@@ -18,6 +18,8 @@ static struct sm_obj_form system = {
 		&legacy_8254_timer,
 		&me_state,
 		&me_state_counter,
+		&me_heci1,
+		&me_pavp,
 		&pciexp_aspm,
 		&pciexp_clk_pm,
 		&pciexp_l1ss,

src/mainboard/google/rex/cfr.c

@@ -15,6 +15,8 @@ static struct sm_obj_form system = {
 		&legacy_8254_timer,
 		&me_state,
 		&me_state_counter,
+		&me_heci1,
+		&me_pavp,
 		&pciexp_aspm,
 		&pciexp_clk_pm,
 		&pciexp_l1ss,

src/mainboard/google/sarien/cfr.c

@@ -21,6 +21,8 @@ static struct sm_obj_form system = {
 		&legacy_8254_timer,
 		&me_state,
 		&me_state_counter,
+		&me_heci1,
+		&me_pavp,
 		&pciexp_aspm,
 		&pciexp_clk_pm,
 		&pciexp_l1ss,

src/mainboard/google/volteer/cfr.c

@@ -29,6 +29,7 @@ static struct sm_obj_form system = {
 		&legacy_8254_timer,
 		&me_state,
 		&me_state_counter,
+		&me_heci1,
 		&pciexp_aspm,
 		&pciexp_clk_pm,
 		&pciexp_l1ss,

src/soc/intel/alderlake/finalize.c

@@ -18,6 +18,7 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/systemagent.h>
 #include <intelblocks/tco.h>
+#include <option.h>
 #include <soc/p2sb.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
@@ -76,7 +77,7 @@ static void tbt_finalize(void)
 static void heci_finalize(void)
 {
 	heci_set_to_d0i3();
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
+	if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT)))
 		heci1_disable();
 }
 

src/soc/intel/alderlake/fsp_params.c

@@ -614,7 +614,7 @@ static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg,
 	/* Check if IGD is present and fill Graphics init param accordingly */
 	s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
 	s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
-	s_cfg->PavpEnable = CONFIG(PAVP);
+	s_cfg->PavpEnable = !!get_uint_option("me_pavp", CONFIG(PAVP));
 }
 
 WEAK_DEV_PTR(tcss_usb3_port1);

src/soc/intel/apollolake/chip.c

@@ -734,7 +734,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 
 	silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
 
-	silconfig->PavpEnable = CONFIG(PAVP);
+	silconfig->PavpEnable = !!get_uint_option("me_pavp", CONFIG(PAVP));
 
 	/* SATA config */
 	if (is_devfn_enabled(PCH_DEVFN_SATA)) {

src/soc/intel/apollolake/cse.c

@@ -8,6 +8,7 @@
 #include <intelblocks/cse.h>
 #include <intelblocks/p2sb.h>
 #include <intelblocks/pcr.h>
+#include <option.h>
 #include <soc/cse.h>
 #include <soc/heci.h>
 #include <soc/iomap.h>
@@ -218,7 +219,7 @@ void heci_cse_lockdown(void)
 	 * It is safe to disable HECI1 now since we won't be talking to the ME
 	 * anymore.
 	 */
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
+	if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT)))
 		heci1_disable();
 }
 

src/soc/intel/cannonlake/finalize.c

@@ -14,6 +14,7 @@
 #include <intelblocks/systemagent.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/thermal.h>
+#include <option.h>
 #include <soc/p2sb.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
@@ -88,7 +89,7 @@ static void soc_finalize(void *unused)
 
 	pch_finalize();
 	apm_control(APM_CNT_FINALIZE);
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) &&
+	if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) &&
 			CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC))
 		heci1_disable();
 

src/soc/intel/cannonlake/fsp_params.c

@@ -734,7 +734,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
 
-	s_cfg->PavpEnable = CONFIG(PAVP);
+	s_cfg->PavpEnable = !!get_uint_option("me_pavp", CONFIG(PAVP));
 
 	/*
 	 * Prevent FSP from programming write-once subsystem IDs by providing

src/soc/intel/cannonlake/smihandler.c

@@ -3,6 +3,7 @@
 #include <device/device.h>
 #include <intelblocks/cse.h>
 #include <intelblocks/smihandler.h>
+#include <option.h>
 #include <soc/soc_chip.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
@@ -16,7 +17,8 @@
  */
 void smihandler_soc_at_finalize(void)
 {
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM))
+	if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) &&
+	    CONFIG(HECI_DISABLE_USING_SMM))
 		heci1_disable();
 }
 

src/soc/intel/common/block/cse/cse.c

@@ -1430,7 +1430,8 @@ static void cse_final_ready_to_boot(void)
 {
 	cse_control_global_reset_lock();
 
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) || cse_is_hfs1_com_soft_temp_disable()) {
+	if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) ||
+	    cse_is_hfs1_com_soft_temp_disable()) {
 		cse_set_to_d0i3();
 		heci1_disable();
 	}

src/soc/intel/common/block/include/intelblocks/cfr.h

@@ -31,6 +31,41 @@ static const struct sm_object me_state_counter = SM_DECLARE_NUMBER({
 	.default_value	= 0,
 });
 
+/* Intel ME HECI1(CSE) device */
+static const struct sm_object me_heci1 = SM_DECLARE_ENUM({
+	.opt_name	= "me_heci1",
+	.ui_name	= "Intel ME HECI1(CSE) device",
+	.ui_helptext	= "Allows to disable HECI1(CSE) device at the end of"
+			  " boot. Disabling this hides the device from the OS,"
+			  " preventing communication with the Intel Management"
+			  " Engine, but it does not disable ME.",
+	.default_value	= !CONFIG(DISABLE_HECI1_AT_PRE_BOOT),
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0		},
+				{ "Enabled",		1		},
+				SM_ENUM_VALUE_END			},
+});
+
+/* Intel ME PAVP (Protected Audio-Video Path) */
+static const struct sm_object me_pavp = SM_DECLARE_ENUM({
+	.opt_name	= "me_pavp",
+	.ui_name	= "Intel ME PAVP",
+	.ui_helptext	= "Enable or disable Intel PAVP (Protected Audio-Video"
+			  " Path). This technology is used to enforce digital"
+			  " rights protections on multimedia content. Streaming"
+			  " or other media playback services may require it to"
+			  " be enabled for correct functioning. You might want"
+			  " to disable this if you do not want DRM content, or"
+			  " if you do not trust the security of the Intel"
+			  " Management Engine, which is where this technology"
+			  " is implemented.",
+	.default_value	= CONFIG(PAVP),
+	.values		= (const struct sm_enum_value[]) {
+				{ "Disabled",		0		},
+				{ "Enabled",		1		},
+				SM_ENUM_VALUE_END			},
+});
+
 /*
  * Power state after power loss
  * Use this option or the one below, but not both

src/soc/intel/elkhartlake/finalize.c

@@ -12,6 +12,7 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/systemagent.h>
 #include <intelblocks/tco.h>
+#include <option.h>
 #include <soc/p2sb.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
@@ -34,7 +35,7 @@ static void pch_finalize(void)
 static void heci_finalize(void)
 {
 	heci_set_to_d0i3();
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
+	if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT)))
 		heci1_disable();
 }
 

src/soc/intel/elkhartlake/smihandler.c

@@ -3,6 +3,7 @@
 #include <device/pci_def.h>
 #include <intelblocks/cse.h>
 #include <intelblocks/smihandler.h>
+#include <option.h>
 #include <soc/soc_chip.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
@@ -16,7 +17,7 @@
  */
 void smihandler_soc_at_finalize(void)
 {
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
+	if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT)))
 		heci1_disable();
 }
 

src/soc/intel/jasperlake/fsp_params.c

@@ -64,7 +64,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	/* Check if IGD is present and fill Graphics init param accordingly */
 	params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
 
-	params->PavpEnable = CONFIG(PAVP);
+	params->PavpEnable = !!get_uint_option("me_pavp", CONFIG(PAVP));
 
 	/* Use coreboot MP PPI services if Kconfig is enabled */
 	if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))

src/soc/intel/jasperlake/smihandler.c

@@ -3,6 +3,7 @@
 #include <device/pci_def.h>
 #include <intelblocks/cse.h>
 #include <intelblocks/smihandler.h>
+#include <option.h>
 #include <soc/soc_chip.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
@@ -16,7 +17,7 @@
  */
 void smihandler_soc_at_finalize(void)
 {
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
+	if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT)))
 		heci1_disable();
 }
 

src/soc/intel/meteorlake/finalize.c

@@ -13,6 +13,7 @@
 #include <intelblocks/systemagent.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/thermal.h>
+#include <option.h>
 #include <spi-generic.h>
 #include <intelpch/lockdown.h>
 #include <soc/p2sb.h>
@@ -55,7 +56,7 @@ static void sa_finalize(void)
 static void heci_finalize(void)
 {
 	heci_set_to_d0i3();
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
+	if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT)))
 		heci1_disable();
 }
 

src/soc/intel/meteorlake/fsp_params.c

@@ -379,7 +379,7 @@ static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg,
 	/* Check if IGD is present and fill Graphics init param accordingly */
 	s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(PCI_DEVFN_IGD);
 	s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
-	s_cfg->PavpEnable = CONFIG(PAVP);
+	s_cfg->PavpEnable = !!get_uint_option("me_pavp", CONFIG(PAVP));
 }
 
 static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,

src/soc/intel/pantherlake/finalize.c

@@ -14,6 +14,7 @@
 #include <intelblocks/tco.h>
 #include <intelblocks/thermal.h>
 #include <intelpch/lockdown.h>
+#include <option.h>
 #include <soc/p2sb.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
@@ -54,7 +55,7 @@ static void sa_finalize(void)
 static void heci_finalize(void)
 {
 	heci_set_to_d0i3();
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
+	if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT)))
 		heci1_disable();
 }
 

src/soc/intel/pantherlake/fsp_params.c

@@ -335,7 +335,7 @@ static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg,
 	/* Check if IGD is present and fill Graphics init param accordingly */
 	s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(PCI_DEVFN_IGD);
 	s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP);
-	s_cfg->PavpEnable = CONFIG(PAVP);
+	s_cfg->PavpEnable = !!get_uint_option("me_pavp", CONFIG(PAVP));
 }
 
 static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,