OpenROAD Integration with eSim-2.5 in Ubuntu-22.04

[RISHABH12005]

Approach

OpenROAD Integration

• Integrated the OpenROAD RTL-to-GDSII flow into the eSim workflow.
• Connected GUI-based execution flow with OpenROAD automation support.
• Added OpenROAD setup and installation support through orfs-setup.py.

File Validation and Workflow Handling

• Implemented .cir.out file selection and validation support.
• Added validation to ensure only valid .cir.out files are processed.
• Added warning and error handling for invalid or missing files.
• Improved project validation and execution handling before starting the OpenROAD flow.

RTL Generation

• Integrated netlist2rtl.py into the workflow.
• Enabled automated Verilog (.v) generation from simulation netlists.
• Added RTL generation support for combinational digital circuits.

RTL-to-GDSII Flow Automation

• Added complete RTL-to-GDSII automation using OpenROAD.
• Integrated synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and GDSII generation stages.
• Added generated .gds file verification after successful flow execution.
• Improved terminal logging and execution monitoring throughout the design flow.

GUI and Layout Visualization

• Added OpenROAD GUI support for testing, debugging, and layout visualization.
• Added KLayout integration support for viewing generated GDSII layouts.
• Added GUI resources, workflow icons, and supporting images.

Design Validation

The complete workflow was validated using the following example designs:

• Half Adder
• Full Adder

The generated outputs were successfully verified using both OpenROAD GUI and KLayout.

FullAdder Generated Files

• FullAdder.cir.out

  • Generated simulation output netlist used as input for RTL generation.

• FullAdder.v

  • Auto-generated Verilog RTL file derived from the .cir.out netlist.

• FullAdder.gds

  • Final GDSII layout generated after completion of the OpenROAD flow.

• FullAdder.def

  • Generated DEF file containing placement and routing information.

• FullAdder.sdc

  • Timing constraint file used during synthesis and timing optimization.

• FullAdder.spef

  • Extracted parasitic file generated after routing.

• logs/

  • Contains execution logs generated during synthesis and physical design stages.

• reports/

  • Contains timing, utilization, routing, and design analysis reports.

HalfAdder Generated Files

• Half_Adder.cir.out

  • Generated simulation output netlist used as input for RTL generation.

• Half_Adder.v

  • Auto-generated Verilog RTL file derived from the .cir.out netlist.

• Half_Adder.gds

  • Final GDSII layout generated after completion of the OpenROAD flow.

• Half_Adder.def

  • Generated DEF file containing placement and routing information.

• Half_Adder.sdc

  • Timing constraint file used during synthesis and timing optimization.

• Half_Adder.spef

  • Extracted parasitic file generated after routing.

• logs/

  • Contains execution logs generated during synthesis and physical design stages.

• reports/

  • Contains timing, utilization, routing, and design analysis reports.

Files Added / Modified

• Application.py

  • Added GUI integration, OpenROAD flow execution handling, and file validation support.

• openroad.py

  • Added OpenROAD flow execution support.
  • Integrated RTL-to-GDSII automation workflow.
  • Added synthesis, floorplanning, placement, CTS, routing, and GDSII generation handling.
  • Added generated file verification and execution logging support.
  • Added OpenROAD GUI launch support for layout verification and debugging.

• orfs-setup.py

  • Added OpenROAD installation and setup support.

• netlist2rtl.py

  • Added netlist-to-RTL conversion functionality.

• OpenROAD flow-related scripts and configuration files

  • Added RTL-to-GDSII automation support and flow configuration handling.

• GUI resource files

  • Added workflow-related icons, images, and supporting assets.

• Example design files

  • Added and validated Half Adder and Full Adder example flows.