ESP32 on the machine framework: LX6 cores, SoC models, DevKitC V4, ESP-IDF boots

.github/workflows/ci.yml

@@ -160,8 +160,9 @@ jobs:
           python3 tests/vendor/freedom-metal/run.py --sdk "$RUNNER_TEMP/freedom-e-sdk" --metal "$RUNNER_TEMP/freedom-metal" --embsim build/${{ matrix.preset }}/bin/embsim
 
   esp-idf:
-    # its own job: ESP-IDF and its RISC-V toolchain take a while to fetch,
-    # and each example is built with idf.py as a user builds it
+    # its own job: ESP-IDF and its RISC-V and Xtensa toolchains take a while
+    # to fetch, and each example is built with idf.py as a user builds it
+    # (the ESP32-C3-DevKitM-1's, and the ESP32-DevKitC's esp32_* ones)
     name: ESP-IDF's examples on the ESP32-C3-DevKitM-1
     runs-on: ubuntu-24.04
     steps:
@@ -174,15 +175,15 @@ jobs:
         run: |
           cmake --preset ci-gcc
           cmake --build --preset ci-gcc
-      - name: ESP-IDF v5.4 and its tools for the ESP32-C3
+      - name: ESP-IDF v5.4 and its tools for the ESP32-C3 and the ESP32
         run: |
           # an origin remote: ESP-IDF's submodules are relative to it (../../espressif/...)
           git init -q "$RUNNER_TEMP/esp-idf"
           git -C "$RUNNER_TEMP/esp-idf" remote add origin https://github.com/espressif/esp-idf.git
           git -C "$RUNNER_TEMP/esp-idf" fetch -q --depth 1 origin 67c1de1eebe095d554d281952fde63c16ee2dca0 # v5.4
           git -C "$RUNNER_TEMP/esp-idf" checkout -q FETCH_HEAD
           git -C "$RUNNER_TEMP/esp-idf" submodule update -q --init --depth 1 --recursive
-          "$RUNNER_TEMP/esp-idf/install.sh" esp32c3
+          "$RUNNER_TEMP/esp-idf/install.sh" esp32c3,esp32
       - name: Run the examples
         run: |
           . "$RUNNER_TEMP/esp-idf/export.sh" >/dev/null

CHANGELOG.md

@@ -5,6 +5,41 @@ versions follow semantic versioning. There is no release yet.
 
 ## Unreleased
 
+### ESP32 in the machine framework: ESP-IDF boots on the ESP32-DevKitC V4
+
+- Added the ESP32's two Xtensa LX6 cores as a framework core
+  (`core/mcu/xtensa/lx6.c`, `lx6fp.c`, backend `xtensa`): the configuration
+  Espressif's core-isa.h gives, windowed registers with their overflow and
+  underflow, loops, XEA2 exceptions, 32 interrupts at their levels, the
+  CCOMPARE timers, MAC16, booleans, the FPU, region protection and the debug
+  option; the APP_CPU held until DPORT releases it, with its own view of the
+  ROM's data pointers.
+- Added `espressif/esp32`: the memory map, the ROM image made from
+  Espressif's ROM ELF (`esprom.py` now places sections that outrun their
+  copy-table entry; the image equals QEMU's esp32-v3-rom.bin), the register
+  file from esp32.svd, and models for DPORT (APP_CPU, caches and flash MMU,
+  interrupt matrix), RTC_CNTL, eFuse, APB_CTRL clocks, GPIO/IO_MUX with
+  strapping, UART0-2, TIMG0/1, SPI0/1 with the GT25Q32A flash, SHA, LEDC,
+  I2C0/1 (master and slave, 16 commands, APB_CLK timing; DPORT's
+  PERIP_RST_EN resets them), the RMT's eight channels, the SAR ADCs
+  through SENS, the two DACs through RTC_IO, the internal analog I2C, RNG and the AHB view.
+- Added the `emblink/esp32_devkitc` board (ESP32-DevKitC V4, WROOM-32E) with
+  its power path, LED, Boot and EN buttons, headers and fixtures.
+- Espressif's ROM, ESP-IDF v5.4's bootloader and hello_world run unmodified
+  through `esp_restart` (`tests/vendor/esp-idf`: `esp32_hello_world` 9/9,
+  `esp32_blink` 6/6, `esp32_ledc_basic` 2/2, `esp32_i2c_eeprom` 3/3 on a
+  24LC256, `esp32_gptimer` 17/17, `esp32_uart_echo` 6/6 on UART2,
+  `esp32_real_time_stats` 10/10 across both cores,
+  `esp32_blink_strip` 7/7 on a WS2812B through the RMT,
+  `esp32_adc_oneshot_read` 6/6 with the eFuse Vref's calibration,
+  `esp32_dac_oneshot` 4/4 (the DACs read back by ADC2); an ADC reads a
+  pin's own DAC on a net with no analog part (the runtime's pin_volts);
+  Arduino-ESP32's AnalogReadSerial, ReadAnalogVoltage, DigitalReadSerial,
+  GetChipID and RepeatTimer for "ESP32 Dev Module" in
+  `tests/vendor/arduino-esp32` (`ESP32_*`); DBREAKC's MASK now marks the
+  address bits compared, as ESP-IDF's stack-end watchpoint has it; the UARTs keep
+  MEM_RX_STATUS's addresses, from which ESP-IDF counts the bytes waiting); `test_lx6` checks the core with programs from Espressif's assembler.
+
 ### Original ESP32 digital per-pin hold
 
 - Added the SDK-mapped digital hold register and per-pad capture masks.