GitHub - Danny552/Processor: A simple processor built in Verilog, made to work with RISC-V Assembler, capable of outputting instructions and memory through VGA in the Intel Altera FPGA Cyclone V Intel DE0-CV

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Processor

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A simple processor built in Verilog, made to work with RISC-V Assembler, capable of outputting instructions and memory through VGA in the Intel Altera FPGA Cyclone V Intel DE0-CV

fpga fpga-programming verilog verilog-project vga

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Name		Name	Last commit message	Last commit date
.qsys_edit		.qsys_edit
MemProgram		MemProgram
db		db
incremental_db		incremental_db
output_files		output_files
simulation/questa		simulation/questa
synthesis		synthesis
vgaClock/synthesis		vgaClock/synthesis
.gitattributes		.gitattributes
ALU.sv		ALU.sv
ALU.sv.bak		ALU.sv.bak
ControlUnit.sv		ControlUnit.sv
ControlUnit.sv.bak		ControlUnit.sv.bak
DataMemory.sv		DataMemory.sv
DataMemory.sv.bak		DataMemory.sv.bak
ImmGen.sv		ImmGen.sv
ImmGen.sv.bak		ImmGen.sv.bak
InstructionMemory.sv		InstructionMemory.sv
InstructionMemory.sv.bak		InstructionMemory.sv.bak
ProgramCounter.sv		ProgramCounter.sv
ProgramCounter.sv.bak		ProgramCounter.sv.bak
ProgramMemory.sv		ProgramMemory.sv
RegisterUnit.sv		RegisterUnit.sv
RegisterUnit.sv.bak		RegisterUnit.sv.bak
build.tcl		build.tcl
c5_pin_model_dump.txt		c5_pin_model_dump.txt
color.qsf		color.qsf
color.qws		color.qws
color.sv		color.sv
color.sv.bak		color.sv.bak
color.v		color.v
color.v.bak		color.v.bak
color_assignment_defaults.qdf		color_assignment_defaults.qdf
font8x16.hex		font8x16.hex
font_renderer.v		font_renderer.v
font_renderer.v.bak		font_renderer.v.bak
font_rom.v		font_rom.v
font_rom.v.bak		font_rom.v.bak
hexa.sv		hexa.sv
processor.qpf		processor.qpf
processor.qsf		processor.qsf
processor.qsf.bak		processor.qsf.bak
processor.qws		processor.qws
processor.sv		processor.sv
processor.sv.bak		processor.sv.bak
processor_nativelink_simulation.rpt		processor_nativelink_simulation.rpt
processor_tb.sv		processor_tb.sv
processor_tb.sv.bak		processor_tb.sv.bak
processor_tb.v		processor_tb.v
program.tcl		program.tcl
vgaClock.bsf		vgaClock.bsf
vgaClock.cmp		vgaClock.cmp
vgaClock.html		vgaClock.html
vgaClock.qsys		vgaClock.qsys
vgaClock.sopcinfo		vgaClock.sopcinfo
vgaClock.xml		vgaClock.xml
vgaClock_generation.rpt		vgaClock_generation.rpt

About

A simple processor built in Verilog, made to work with RISC-V Assembler, capable of outputting instructions and memory through VGA in the Intel Altera FPGA Cyclone V Intel DE0-CV

fpga fpga-programming verilog verilog-project vga

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